| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | InstructionCost.h | 112 InstructionCost RHS2(RHS);
113 *this += RHS2;
129 InstructionCost RHS2(RHS);
130 *this -= RHS2;
152 *this *= RHS2;
164 *this /= RHS2;
211 return *this == RHS2;
224 return *this < RHS2;
229 return *this > RHS2;
234 return *this <= RHS2;
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 241 const SparseBitVectorElement &RHS2, in intersectWithComplement()
247 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; in intersectWithComplement()
689 const SparseBitVector<ElementSize> &RHS2) in intersectWithComplement() argument
692 intersectWithComplement(RHS2); in intersectWithComplement()
694 } else if (this == &RHS2) { in intersectWithComplement()
695 SparseBitVector RHS2Copy(RHS2); in intersectWithComplement()
703 ElementListConstIter Iter2 = RHS2.Elements.begin(); in intersectWithComplement()
711 while (Iter2 != RHS2.Elements.end()) { in intersectWithComplement()
735 const SparseBitVector<ElementSize> *RHS2) { in intersectWithComplement() argument
736 intersectWithComplement(*RHS1, *RHS2); in intersectWithComplement()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2428 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2430 !MatchICmpAgainstInvariant(Cond2, P2, LHS2, RHS2)) in hoistMinMax()
2451 RHS2 = Builder.CreateFreeze(RHS2, RHS2->getName() + ".fr"); in hoistMinMax()
2453 id, RHS1, RHS2, nullptr, StringRef("invariant.") + in hoistMinMax()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3577 Value *LHS2, *RHS2; in visitSelectInst() local
3578 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor) in visitSelectInst()
3580 RHS2, SI, SPF, RHS)) in visitSelectInst()
3582 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor) in visitSelectInst()
3584 RHS2, SI, SPF, LHS)) in visitSelectInst()
|
| H A D | InstCombineCompares.cpp | 3083 Value *LHS2, *RHS2; in matchThreeWayIntCompare() local
3084 if (!match(UnequalVal, m_Select(m_ICmp(PredB, m_Value(LHS2), m_Value(RHS2)), in matchThreeWayIntCompare()
3091 std::swap(LHS2, RHS2); in matchThreeWayIntCompare()
3097 if (PredB == ICmpInst::ICMP_SGT && isa<Constant>(RHS2)) { in matchThreeWayIntCompare()
3101 PredB, cast<Constant>(RHS2)); in matchThreeWayIntCompare()
3106 RHS2 = FlippedStrictness->second; in matchThreeWayIntCompare()
3111 return PredB == ICmpInst::ICMP_SLT && RHS == RHS2; in matchThreeWayIntCompare()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 3199 const Value *LHS2 = nullptr, *RHS2 = nullptr; in isSignedMinMaxClamp() local
3200 SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor; in isSignedMinMaxClamp()
3204 if (!match(RHS2, m_APInt(CHigh))) in isSignedMinMaxClamp()
8444 const Value *RHS1, *RHS2; in isImpliedCondition() local
8445 if (match(RHS, m_LogicalOr(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
8451 isImpliedCondition(LHS, RHS2, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
8455 if (match(RHS, m_LogicalAnd(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
8461 isImpliedCondition(LHS, RHS2, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 845 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, in getAVRCmp() local
858 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); in getAVRCmp()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5679 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
5681 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
5683 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); in OptimizeVFPBrcond()
5687 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12228 Register RHS2 = MI.getOperand(4).getReg(); in EmitInstrWithCustomInserter() local
12234 .addReg(LHS2).addReg(RHS2) in EmitInstrWithCustomInserter()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7039 SDValue RHS2 = Val.getOperand(1); in matchSetCC() local
7042 if (LHS == LHS2 && RHS == RHS2) { in matchSetCC()
7047 } else if (LHS == RHS2 && RHS == LHS2) { in matchSetCC()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22939 SDValue RHS1, RHS2; in splitIntVSETCC() local
22940 std::tie(RHS1, RHS2) = splitVector(RHS, DAG, dl); in splitIntVSETCC()
22947 DAG.getNode(ISD::SETCC, dl, HiVT, LHS2, RHS2, CC)); in splitIntVSETCC()
|