| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 240 void intersectWithComplement(const SparseBitVectorElement &RHS1, in intersectWithComplement()
247 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; in intersectWithComplement()
688 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1, in intersectWithComplement() argument
691 if (this == &RHS1) { in intersectWithComplement()
696 intersectWithComplement(RHS1, RHS2Copy); in intersectWithComplement()
702 ElementListConstIter Iter1 = RHS1.Elements.begin(); in intersectWithComplement()
707 if (RHS1.Elements.empty()) in intersectWithComplement()
712 if (Iter1 == RHS1.Elements.end()) in intersectWithComplement()
731 std::copy(Iter1, RHS1.Elements.end(), std::back_inserter(Elements)); in intersectWithComplement()
734 void intersectWithComplement(const SparseBitVector<ElementSize> *RHS1, in intersectWithComplement() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1323 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1340 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1343 std::swap(RHS0, RHS1); in foldLogicOfFCmps()
1360 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
3106 Value *RHS1 = RHS->getOperand(1); in foldAndOrOfICmpEqConstantAndICmp() local
3130 Other = RHS1; in foldAndOrOfICmpEqConstantAndICmp()
3162 match(RHS1, m_APInt(RHSC)); in foldAndOrOfICmps()
3167 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldAndOrOfICmps()
3171 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldAndOrOfICmps()
3980 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldXorOfICmps()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 724 ConstantInt *RHS0, *RHS1; in mergeChecks() local
733 m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in mergeChecks()
738 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue()); in mergeChecks()
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| H A D | LICM.cpp | 2428 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2429 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2453 id, RHS1, RHS2, nullptr, StringRef("invariant.") + in hoistMinMax()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1852 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); in simplifyAndOrOfFCmps() local
1870 if (((LHS1 == RHS0 || LHS1 == RHS1) && in simplifyAndOrOfFCmps()
1872 ((LHS0 == RHS0 || LHS0 == RHS1) && in simplifyAndOrOfFCmps()
1884 if (((RHS1 == LHS0 || RHS1 == LHS1) && in simplifyAndOrOfFCmps()
1887 isKnownNeverNaN(RHS1, DL, TLI, 0, Q.AC, Q.CxtI, Q.DT))) in simplifyAndOrOfFCmps()
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| H A D | ValueTracking.cpp | 8444 const Value *RHS1, *RHS2; in isImpliedCondition() local
8445 if (match(RHS, m_LogicalOr(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
8447 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
8455 if (match(RHS, m_LogicalAnd(m_Value(RHS1), m_Value(RHS2)))) { in isImpliedCondition()
8457 isImpliedCondition(LHS, RHS1, DL, LHSIsTrue, Depth + 1)) in isImpliedCondition()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 843 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, in getAVRCmp() local
857 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6167 SDValue RHS1 = RHS->getOperand(1); in foldAndOrOfSETCC() local
6171 auto *RHS1C = isConstOrConstSplat(RHS1); in foldAndOrOfSETCC()
6209 Operand2 = RHS1; in foldAndOrOfSETCC()
6211 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6219 if (LHS0 == RHS1) { in foldAndOrOfSETCC()
6227 Operand2 = RHS1; in foldAndOrOfSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5679 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
5681 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
5687 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12227 Register RHS1 = MI.getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
12231 .addReg(RHS1) in EmitInstrWithCustomInserter()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22939 SDValue RHS1, RHS2; in splitIntVSETCC() local
22940 std::tie(RHS1, RHS2) = splitVector(RHS, DAG, dl); in splitIntVSETCC()
22946 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
47460 SDValue RHS1 = RHS.getOperand(1); in combineVectorHADDSUB() local
47462 (RHS0 == RHS1 || RHS0.isUndef() || RHS1.isUndef())) { in combineVectorHADDSUB()
47466 RHS0.isUndef() ? RHS1 : RHS0); in combineVectorHADDSUB()
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