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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td19 bits<5> RB;
25 let Inst{16-20} = RB;
32 let RB = 0;
46 bits<5> RB;
51 let Inst{16-20} = RB;
60 bits<5> RB;
66 let Inst{16-20} = RB;
73 let RB = 0;
87 bits<5> RB;
94 let Inst{16-20} = RB;
[all …]
H A DPPCInstrDFP.td48 "dcmpu $BF, $RA, $RB", IIC_FPCompare>;
51 "dcmpuq $BF, $RA, $RB", IIC_FPCompare>;
54 "dcmpo $BF, $RA, $RB", IIC_FPCompare>;
57 "dcmpoq $BF, $RA, $RB", IIC_FPCompare>;
98 "drsp", "$RST, $RB", IIC_FPGeneral, []>;
134 "dxex", "$RST, $RB", NoItinerary, []>;
136 "dxexq", "$RST, $RB", NoItinerary, []>;
138 (ins f8rc:$RA, f8rc:$RB),
139 "diex", "$RST, $RA, $RB", []>;
141 (ins f8rc:$RA, fpairrc:$RB),
[all …]
H A DPPCInstrFuture.td19 bits<5> RB;
28 let Inst{16-20} = RB;
50 (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
51 "subfus", "$RT, $L, $RA, $RB", []>;
57 "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
60 "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
63 (ins memr:$RA, g8rc:$RB),
67 (ins memr:$RA, g8rc:$RB),
73 (ins vsrc:$XT, memr:$RA, g8rc:$RB),
77 (ins vsrc:$XT, memr:$RA, g8rc:$RB),
[all …]
H A DPPCInstr64Bit.td642 "or", "$RA, $RST, $RB", IIC_IntSimple,
693 "add $RT, $RA, $RB", IIC_IntSimple,
901 (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB",
1001 "cmpb $RA, $RST, $RB", IIC_IntGeneral,
1312 (ins (memrr $RA, $RB):$addr),
1317 (ins (memrr $RA, $RB):$addr),
1373 (ins (memrr $RA, $RB):$addr),
1378 (ins (memrr $RA, $RB):$addr),
1383 (ins (memrr $RA, $RB):$addr),
1442 (ins (memrr $RA, $RB):$addr),
[all …]
H A DPPCInstrHTM.td41 let RB = 0;
45 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
46 "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
55 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
56 "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
73 let RB = 0;
81 let RB = 0;
106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
[all …]
H A DPPCInstrInfo.td2007 (ins (memrr $RA, $RB):$addr),
2013 (ins (memrr $RA, $RB):$addr),
2019 (ins (memrr $RA, $RB):$addr),
4240 "mtsrin $RS, $RB", IIC_SprMTSR>;
4243 "mfsrin $RS, $RB", IIC_SprMFSR>;
4344 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
4347 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",
4688 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4701 def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
4703 def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;
[all …]
H A DPPCInstrFormats.td442 bits<5> RB;
485 bits<5> RB;
515 let RB = 0;
557 let RB = 0;
567 bits<5> RB;
583 bits<5> RB;
617 bits<5> RB;
646 bits<5> RB;
916 let RB = 0;
987 bits<5> RB;
[all …]
H A DPPCInstrAltivec.td270 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
278 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
286 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
288 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
346 let RB = 0;
354 let RB = 0;
391 [(int_ppc_altivec_dstst i64:$RA, i32:$RB,
460 "vmaddfp $RT, $RA, $RC, $RB", IIC_VecFP,
462 (fma v4f32:$RA, v4f32:$RC, v4f32:$RB))]>;
466 "vnmsubfp $RT, $RA, $RC, $RB", IIC_VecFP,
[all …]
H A DPPCExpandAtomicPseudoInsts.cpp156 Register RB = MI.getOperand(3).getReg(); in expandAtomicRMW128() local
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
204 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
235 Register RB = MI.getOperand(3).getReg(); in expandAtomicCmpSwap128() local
263 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
283 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
H A DPPCInstrP10.td378 // VX-Form: [PO VRT RA RB XO].
574 let RB = 0;
834 bits<5> RB;
840 let Inst{16-20} = RB;
1619 "vextdubvlx $RT, $RA, $RB, $RC",
1627 "vextdubvrx $RT, $RA, $RB, $RC",
1635 "vextduhvlx $RT, $RA, $RB, $RC",
1643 "vextduhvrx $RT, $RA, $RB, $RC",
1651 "vextduwvlx $RT, $RA, $RB, $RC",
1667 "vextddvlx $RT, $RA, $RB, $RC",
[all …]
H A DPPCInstrVSX.td262 // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
269 // [PO S RA RB XO SX]
1409 f128:$RA, f128:$RB))]>;
1485 f128:$RB))]>;
1491 [(set f128:$RST, (PPCany_fctidz f128:$RB))]>;
1493 [(set f128:$RST, (PPCany_fctiwz f128:$RB))]>;
1495 [(set f128:$RST, (PPCany_fctiduz f128:$RB))]>;
1497 [(set f128:$RST, (PPCany_fctiwuz f128:$RB))]>;
1695 "lxvl $XT, $addr, $RB", IIC_LdStLoad,
1741 i64:$RB)]>;
[all …]
/freebsd-14.2/contrib/llvm-project/clang/lib/Rewrite/
H A DHTMLRewrite.cpp62 RB.InsertTextAfter(B, StartTag); in HighlightRange()
63 RB.InsertTextBefore(E, EndTag); in HighlightRange()
96 RB.InsertTextAfter(i, StartTag); in HighlightRange()
133 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText()
142 RB.ReplaceText(FilePos, 1, in EscapeText()
151 RB.ReplaceText(FilePos, 1, "&lt;"); in EscapeText()
156 RB.ReplaceText(FilePos, 1, "&gt;"); in EscapeText()
220 RB.InsertTextBefore(B, OS.str()); in AddLineNumber()
222 RB.InsertTextBefore(B, OS.str()); in AddLineNumber()
223 RB.InsertTextBefore(E, "</td></tr>"); in AddLineNumber()
[all …]
H A DRewriter.cpp158 const RewriteBuffer &RB = I->second; in getRangeSize() local
159 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange); in getRangeSize()
160 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange); in getRangeSize()
209 const RewriteBuffer &RB = I->second; in getRewrittenText() local
210 EndOff = RB.getMappedOffset(EndOff, true); in getRewrittenText()
211 StartOff = RB.getMappedOffset(StartOff); in getRewrittenText()
219 RewriteBuffer::iterator Start = RB.begin(); in getRewrittenText()
395 RewriteBuffer &RB = getEditBuffer(FID); in IncreaseIndentation() local
403 RB.InsertText(offs, indent, /*InsertAfter=*/false); in IncreaseIndentation()
/freebsd-14.2/contrib/llvm-project/clang/lib/Frontend/Rewrite/
H A DRewriteMacros.cpp94 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local
133 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
139 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
169 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); in RewriteMacrosInInput()
187 RB.InsertTextBefore(EndPos, "*/"); in RewriteMacrosInInput()
203 RB.InsertTextBefore(InsertPos, Expansion); in RewriteMacrosInInput()
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_ring_buffer.h27 RingBuffer *RB = reinterpret_cast<RingBuffer*>(Ptr); in New() local
29 RB->last_ = RB->next_ = reinterpret_cast<T*>(End - sizeof(T)); in New()
30 return RB; in New()
/freebsd-14.2/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DMacOSXAPIChecker.cpp79 const MemRegion *RB = R->getBaseRegion(); in CheckDispatchOnce() local
80 const MemSpaceRegion *RS = RB->getMemorySpace(); in CheckDispatchOnce()
98 if (const VarRegion *VR = dyn_cast<VarRegion>(RB)) { in CheckDispatchOnce()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp354 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { in addNodeIDRegType()
355 ID.AddPointer(RB); in addNodeIDRegType()
397 if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB)) in addNodeIDReg() local
398 addNodeIDRegType(RB); in addNodeIDReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp310 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
311 if (RB == &PPC::FPRRegBank) in hasFPConstraints()
313 if (RB == &PPC::GPRRegBank) in hasFPConstraints()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp175 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
185 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
256 RC = getRegClass(Ty, RB); in selectDebugInstr()
454 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
457 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
460 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
462 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
470 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
472 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
559 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp94 if (auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank)) in getRegBank() local
95 return RB; in getRegBank()
142 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister() local
144 if (RB && !RB->covers(RC)) in constrainGenericRegister()
/freebsd-14.2/sys/contrib/openzfs/module/lua/
H A Dlvm.c551 #define RB(i) check_exp(getBMode(GET_OPCODE(i)) == OpArgR, base+GETARG_B(i)) macro
618 setobjs2s(L, ra, RB(i)); in luaV_execute()
649 Protect(luaV_gettable(L, RB(i), RKC(i), ra)); in luaV_execute()
673 StkId rb = RB(i); in luaV_execute()
699 TValue *rb = RB(i); in luaV_execute()
709 TValue *rb = RB(i); in luaV_execute()
714 Protect(luaV_objlen(L, ra, RB(i))); in luaV_execute()
764 TValue *rb = RB(i); in luaV_execute()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Rewrite/Core/
H A DHTMLRewrite.h47 void HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h153 bool alias(RegisterRef RA, RegisterRef RB) const;
220 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
222 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
/freebsd-14.2/contrib/llvm-project/clang/lib/Frontend/
H A DPrecompiledPreamble.cpp649 for (const auto &RB : PreprocessorOpts.RemappedFileBuffers) { in CanReuse() local
651 PreambleFileHash::createForMemoryBuffer(RB.second->getMemBufferRef()); in CanReuse()
653 if (moveOnNoError(VFS.status(RB.first), Status)) in CanReuse()
656 OverridenFileBuffers[RB.first] = PreambleHash; in CanReuse()
658 llvm::SmallString<128> MappedPath(RB.first); in CanReuse()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp564 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
576 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
600 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
663 switch (RB.getID()) { in getMinSizeForRegBank()
977 RC = getRegClassForTypeOnBank(Ty, RB); in selectDebugInstr()
2965 MRI.setRegBank(NewDst, RB); in select()
3970 if (RB.getID() != AArch64::GPRRegBankID) in selectMergeValues()
4366 if (RB.getID() == AArch64::GPRRegBankID) { in getInsertVecEltOpInfo()
5302 if (RB.getID() == AArch64::FPRRegBankID) { in emitLaneInsert()
7747 if (RB != DstRB) { in fixupPHIOpBanks()
[all …]

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