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Searched refs:RA (Results 1 – 25 of 154) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
38 let RA = 0;
45 bits<5> RA;
50 let Inst{11-15} = RA;
59 bits<5> RA;
65 let Inst{11-15} = RA;
79 let RA = 0;
86 bits<5> RA;
102 bits<5> RA;
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H A DPPCInstr64Bit.td901 (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB",
969 [(set i64:$RA,
1085 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA),
1107 (outs g8rc:$RA),
1114 (outs gprc:$RA),
1133 defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA),
1138 defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA),
1145 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA),
1304 (ins (memri $D, $RA):$addr),
1357 (ins (memri $D, $RA):$addr),
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H A DPPCInstrFuture.td18 bits<5> RA;
27 let Inst{11-15} = RA;
50 (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
51 "subfus", "$RT, $L, $RA, $RB", []>;
57 "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
60 "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
63 (ins memr:$RA, g8rc:$RB),
67 (ins memr:$RA, g8rc:$RB),
73 (ins vsrc:$XT, memr:$RA, g8rc:$RB),
77 (ins vsrc:$XT, memr:$RA, g8rc:$RB),
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H A DPPCInstrDFP.td48 "dcmpu $BF, $RA, $RB", IIC_FPCompare>;
51 "dcmpuq $BF, $RA, $RB", IIC_FPCompare>;
54 "dcmpo $BF, $RA, $RB", IIC_FPCompare>;
57 "dcmpoq $BF, $RA, $RB", IIC_FPCompare>;
112 let RA = 1 in
138 (ins f8rc:$RA, f8rc:$RB),
139 "diex", "$RST, $RA, $RB", []>;
141 (ins f8rc:$RA, fpairrc:$RB),
142 "diexq", "$RST, $RA, $RB", []>;
174 "dtstex $BF, $RA, $RB", IIC_FPCompare>;
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H A DPPCInstrHTM.td38 (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,
69 (outs), (ins gprc:$RA), "treclaim. $RA",
80 let RA = 0;
106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_treclaim i32:$RA),
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H A DPPCMacroFusion.cpp105 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints() local
106 if (!RA.isReg()) in checkOpConstraints()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
205 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
209 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
216 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
220 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
H A DPPCInstrP10.td188 bits<5> RA;
210 bits<5> RA;
262 bits<5> RA;
286 bits<5> RA;
573 let RA = BI;
588 let RA = 0 in
605 let RA = 0 in
622 let RA = 0 in
817 bits<5> RA;
833 bits<5> RA;
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H A DPPCInstrInfo.td2007 (ins (memrr $RA, $RB):$addr),
2013 (ins (memrr $RA, $RB):$addr),
2019 (ins (memrr $RA, $RB):$addr),
2025 (ins (memrr $RA, $RB):$addr),
2032 (ins (memrr $RA, $RB):$addr),
3085 defm RLWIMI : MForm_2r<20, (outs gprc:$RA),
3102 defm RLWNM : MForm_1r<23, (outs gprc:$RA),
4344 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
4347 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB",
4701 def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
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H A DPPCInstrFormats.td241 bits<5> RA;
296 let RA = 0;
305 let RA = R;
336 let RA = 0;
404 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
409 bits<5> RA;
426 bits<5> RA;
441 bits<5> RA;
483 bits<5> RA;
514 let RA = 0;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocPriorityAdvisor.cpp58 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
60 MF, RA, &getAnalysis<SlotIndexes>()); in getAdvisor()
105 const RAGreedy &RA, in RegAllocPriorityAdvisor() argument
107 : RA(RA), LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()), in RegAllocPriorityAdvisor()
109 RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes), in RegAllocPriorityAdvisor()
111 RA.getRegClassPriorityTrumpsGlobalness()), in RegAllocPriorityAdvisor()
112 ReverseLocalAssignment(RA.getReverseLocalAssignment()) {} in RegAllocPriorityAdvisor()
H A DRegAllocEvictionAdvisor.cpp80 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
81 return std::make_unique<DefaultEvictionAdvisor>(MF, RA); in getAdvisor()
126 const RAGreedy &RA) in RegAllocEvictionAdvisor() argument
127 : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()), in RegAllocEvictionAdvisor()
128 LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()), in RegAllocEvictionAdvisor()
130 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
151 bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill; in shouldEvict()
201 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost()
223 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in canEvictInterferenceBasedOnCost()
238 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in canEvictInterferenceBasedOnCost()
H A DRDFGraph.cpp113 OS << Print(RA.Id, G) << '<' << Print(RA.Addr->getRegRef(G), G) << '>'; in printRefHeader()
789 Ref RA = NA; in cloneNode() local
1140 NodeId Start = RA.Id; in getRelatedRefs()
1142 Refs.push_back(RA); in getRelatedRefs()
1143 RA = getNextRelated(IA, RA); in getRelatedRefs()
1144 } while (RA.Id != 0 && RA.Id != Start); in getRelatedRefs()
1208 NodeId Start = RA.Id; in locateNextRef()
1215 RA = NA; in locateNextRef()
1587 return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering); in linkBlockRefs()
1590 return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering); in linkBlockRefs()
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H A DMLRegAllocPriorityAdvisor.cpp93 MLPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA,
141 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
153 MF, RA, &getAnalysis<SlotIndexes>(), Runner.get()); in getAdvisor()
178 DevelopmentModePriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA, in DevelopmentModePriorityAdvisor() argument
181 : MLPriorityAdvisor(MF, RA, Indexes, Runner), Log(Log) {} in DevelopmentModePriorityAdvisor()
260 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
268 MF, RA, &getAnalysis<SlotIndexes>(), Runner.get(), Log.get()); in getAdvisor()
286 const RAGreedy &RA, in MLPriorityAdvisor() argument
289 : RegAllocPriorityAdvisor(MF, RA, Indexes), DefaultAdvisor(MF, RA, Indexes), in MLPriorityAdvisor()
297 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriorityImpl()
H A DRegAllocPriorityAdvisor.h34 RegAllocPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA,
38 const RAGreedy &RA;
51 DefaultPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA, in DefaultPriorityAdvisor() argument
53 : RegAllocPriorityAdvisor(MF, RA, Indexes) {} in DefaultPriorityAdvisor()
69 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
H A DRegAllocEvictionAdvisor.h122 RegAllocEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA);
138 const RAGreedy &RA; variable
177 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
206 DefaultEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA) in DefaultEvictionAdvisor() argument
207 : RegAllocEvictionAdvisor(MF, RA) {} in DefaultEvictionAdvisor()
H A DMLRegAllocEvictAdvisor.cpp288 MLEvictAdvisor(const MachineFunction &MF, const RAGreedy &RA,
396 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
408 MF, RA, Runner.get(), getAnalysis<MachineBlockFrequencyInfo>(), in getAdvisor()
435 : MLEvictAdvisor(MF, RA, Runner, MBFI, Loops), Log(Log) {} in DevelopmentModeEvictAdvisor()
540 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
546 MF, RA, Runner.get(), getAnalysis<MachineBlockFrequencyInfo>(), in getAdvisor()
573 : RegAllocEvictionAdvisor(MF, RA), DefaultAdvisor(MF, RA), in MLEvictAdvisor()
636 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in loadInterferenceFeatures()
645 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in loadInterferenceFeatures()
774 static_cast<float>(RA.getQueueSize()) / InitialQSize; in tryFindEvictionCandidate()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFDeadCode.cpp90 if (!LiveNodes.count(RA.Id)) in scanInstr()
91 WorkQ.push_back(RA.Id); in scanInstr()
136 auto RA = DFG.addr<RefNode*>(N); in collect() local
137 if (DFG.IsDef(RA)) in collect()
138 processDef(RA, WorkQ); in collect()
140 processUse(RA, WorkQ); in collect()
162 DeadNodes.insert(RA.Id); in collect()
224 if (DFG.IsUse(RA)) in erase()
225 DFG.unlinkUse(RA, true); in erase()
226 else if (DFG.IsDef(RA)) in erase()
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H A DHexagonRDFOpt.cpp168 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
169 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
170 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
203 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
204 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
208 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
209 unsigned N = OpMap[RA.Id]; in removeOperand()
211 RA.Addr->setRegRef(&MI->getOperand(N), DFG); in removeOperand()
213 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG); in removeOperand()
/freebsd-14.2/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt3 The Ring Accelerator (RA) is a machine which converts read/write accesses
5 circular data structure in memory. The RA eliminates the need for each DMA
9 source interface on the RA) and the RA replaces the address for the transaction
14 management of the packet queues. The K3 SoCs can have more than one RA instances
21 "rt" - The RA Ring Real-time Control/Status Registers
22 "fifos" - The RA Queues Registers
23 "proxy_gcfg" - The RA Proxy Global Config Registers
24 "proxy_target" - The RA Proxy Datapath Registers
25 - ti,num-rings : Number of rings supported by RA
H A Dk3-ringacc.yaml15 The Ring Accelerator (RA) is a machine which converts read/write accesses
17 circular data structure in memory. The RA eliminates the need for each DMA
21 source interface on the RA) and the RA replaces the address for the transaction
26 management of the packet queues. The K3 SoCs can have more than one RA instances
54 description: Number of rings supported by RA
/freebsd-14.2/contrib/lua/src/
H A Dlvm.c905 StkId ra = RA(i); \
934 StkId ra = RA(i); \
944 StkId ra = RA(i); \
954 StkId ra = RA(i); \
984 StkId ra = RA(i); \
998 StkId ra = RA(i); \
1013 StkId ra = RA(i); \
1033 StkId ra = RA(i); \
1189 StkId ra = RA(i); in luaV_execute()
1194 StkId ra = RA(i); in luaV_execute()
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/freebsd-14.2/crypto/openssl/crypto/bn/asm/
H A Dbn-c64xplus.asm38 .asg B3,RA
54 [!B0] BNOP RA
76 BNOP RA,4
84 [!B0] BNOP RA
102 BNOP RA,4
110 [!B0] BNOP RA
128 BNOP RA,5
135 [!B0] BNOP RA
153 BNOP RA,5
178 BNOP RA,4
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Object/
H A DRelocationResolver.cpp468 int64_t RA = Addend; in resolveRISCV() local
474 return (S + RA) & 0xFFFFFFFF; in resolveRISCV()
478 return S + RA; in resolveRISCV()
484 return (S + RA) & 0xFF; in resolveRISCV()
486 return (A + (S + RA)) & 0xFF; in resolveRISCV()
488 return (A - (S + RA)) & 0xFF; in resolveRISCV()
490 return (S + RA) & 0xFFFF; in resolveRISCV()
492 return (A + (S + RA)) & 0xFFFF; in resolveRISCV()
496 return (S + RA) & 0xFFFFFFFF; in resolveRISCV()
502 return (A + (S + RA)); in resolveRISCV()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DDeadArgumentElimination.h130 bool isLive(const RetOrArg &RA);
131 void markValue(const RetOrArg &RA, Liveness L,
133 void markLive(const RetOrArg &RA);
135 void propagateLiveness(const RetOrArg &RA);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp666 markLive(RA); in markValue()
669 assert(!isLive(RA) && "Use is already live!"); in markValue()
673 markLive(RA); in markValue()
678 Uses.emplace(MaybeLiveUse, RA); in markValue()
703 if (isLive(RA)) in markLive()
706 LiveValues.insert(RA); in markLive()
709 << RA.getDescription() << " live\n"); in markLive()
710 propagateLiveness(RA); in markLive()
714 return LiveFunctions.count(RA.F) || LiveValues.count(RA); in isLive()
723 UseMap::iterator Begin = Uses.lower_bound(RA); in propagateLiveness()
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