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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td62 def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>, DwarfRegNum<[7]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S65 #define mantexpd R7:6
72 #define zero R7:6
200 #define mantexpd R7:6
207 #define zero R7:6
329 #define mantexpd R7:6
334 #define zero0 R7:6
H A Dfastmath2_dlib_asm.S63 #define mantexpd R7:6
164 #define mantexpd R7:6
266 #define mantexpd R7:6
267 #define mantdh R7
378 #define c07f R7
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp217 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
222 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
286 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
288 def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
292 def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
309 R7, R6, R5, R4,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
322 // Also save R7-R4 first to match the stack frame fixed spill areas.
323 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
331 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
[all …]
H A DARMBaseRegisterInfo.h51 case R4: case R5: case R6: case R7: in isARMArea1Register()
80 case R4: case R5: case R6: case R7: in isSplitFPArea1Register()
H A DARMSubtarget.h439 return ARM::R7; in getFramePointerReg()
450 return (getFramePointerReg() == ARM::R7 && in splitFramePushPop()
H A DThumb1FrameLowering.cpp239 case ARM::R7: in emitPrologue()
379 case ARM::R7: in emitPrologue()
716 if (STI.getFramePointerReg() == ARM::R7) in emitPopSpecialFixUp()
717 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
839 ARM::R7, ARM::LR};
844 ARM::R5, ARM::R6, ARM::R7, ARM::LR};
H A DARMSLSHardening.cpp141 {"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
155 {"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
H A DLanaiRegisterInfo.td48 R6, R7, R18, R19, // registers for passing arguments
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp74 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
99 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
150 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
H A DPPCCallingConv.td78 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
89 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
223 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
238 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd-14.2/contrib/arm-optimized-routines/pl/math/
H A Derfc_1u8.c34 #define R7 -0x1.8e38e38e38e39p-3 macro
109 double p8 = fma (Q7 * r, p7, p6) * R7; in erfc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFFrameLowering.cpp36 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td43 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
92 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
122 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h59 case Lanai::R7: in getLanaiRegisterNumbering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
168 // Register class for R0 - R7.
169 // Some 16-bit integer instructions can only access R0 - R7.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCCallingConv.td32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Daspeed-bmc-qcom-dc-scm-v1.dts112 /*R0-R7*/ "","","","","","","","",
H A Daspeed-bmc-vegman-n110.dts32 /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()

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