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Searched refs:R12 (Results 1 – 25 of 70) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
H A DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td67 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>, DwarfRegNum<[12]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
H A DMSP430ISelLowering.cpp460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
784 unsigned R12 = MSP430::R12; in LowerReturn() local
786 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Glue); in LowerReturn()
788 RetOps.push_back(DAG.getRegister(R12, PtrVT)); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
81 case R8: case R9: case R10: case R12: in isSplitFPArea1Register()
H A DARMRegisterInfo.td93 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
235 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
245 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
264 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
285 (add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))];
332 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))];
369 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
385 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
536 [(add R12), (add SP)]>;
543 // Register class representing a pair of even-odd GPRs, except (R12, SP).
H A DARMCallingConv.td164 // The 'nest' parameter, if any, is passed in R12.
165 CCIfNest<CCAssignToReg<[R12]>>,
335 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
344 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
361 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
H A DARMExpandPseudoInsts.cpp1309 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1348 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1350 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1351 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1355 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1356 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1361 .addReg(ARM::R12) in CMSEClearFPRegsV8()
2081 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
2111 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
2277 return !Op.isReg() || Op.getReg() != ARM::R12; in ExpandMI()
[all …]
H A DThumb1FrameLowering.cpp368 case ARM::R12: in emitPrologue()
402 case ARM::R12: { in emitPrologue()
991 .addReg(ARM::R12, RegState::Define) in popRegsFromStack()
1035 .addReg(ARM::R12, RegState::Kill) in popRegsFromStack()
H A DARMFrameLowering.cpp813 case ARM::R12: in emitPrologue()
836 case ARM::R12: in emitPrologue()
1011 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
1017 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
1131 case ARM::R12: in emitPrologue()
1164 case ARM::R12: in emitPrologue()
1167 Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true); in emitPrologue()
2854 CalleeSavedInfo(ARM::R12)); in assignCalleeSavedSpillSlots()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td48 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
89 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd-14.2/sys/cddl/dev/dtrace/arm/
H A Dregset.h46 #define REG_SP R12
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
385 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
424 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
547 // A SwiftError is passed in R12.
548 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
644 // A SwiftError is passed in R12.
645 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
1122 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1124 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp158 StackSlotsUsedByFunclet = Last - ARC::R12; in emitPrologue()
270 StackSlotsUsedByFunclet = Last - ARC::R12; in emitEpilogue()
372 for (unsigned Which = Last; Which > ARC::R12; Which--) { in assignCalleeSavedSpillSlots()
385 if (I.getReg() > ARC::R12) in assignCalleeSavedSpillSlots()
H A DARCRegisterInfo.td78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h72 case Lanai::R12: in getLanaiRegisterNumbering()
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_dlib_asm.S265 #define c8001 R12
272 #define mantal_ R12
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp239 Value *R11, *R12; in getMaskedTypeForICmpPair() local
244 D = R12; in getMaskedTypeForICmpPair()
245 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
246 A = R12; in getMaskedTypeForICmpPair()
259 R12 = Constant::getAllOnesValue(R1->getType()); in getMaskedTypeForICmpPair()
264 D = R12; in getMaskedTypeForICmpPair()
267 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
268 A = R12; in getMaskedTypeForICmpPair()
288 D = R12; in getMaskedTypeForICmpPair()
291 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp445 Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; in findScratchRegister() local
453 *SR2 = R12; in findScratchRegister()
480 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) in findScratchRegister()
655 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue()
1580 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitEpilogue()
2468 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) in spillCalleeSavedRegisters()
2473 .addReg(PPC::R12, in spillCalleeSavedRegisters()
2532 unsigned MoveReg = PPC::R12; in restoreCRs()
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/asan/
H A Dasan_rtl_x86_64.S143 ASAN_MEMORY_ACCESS_CALLBACKS_ADD(R12)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dam335x-boneblue.dts265 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */
489 "EQEP_2B", /* R12 */
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h296 ENTRY(R12) \
330 ENTRY(R12) \
/freebsd-14.2/sys/amd64/amd64/
H A Dbpf_jit_machdep.h52 #define R12 4 macro

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