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Searched refs:Qd (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrMVE.td1408 bits<4> Qd;
1506 bits<4> Qd;
1689 bits<4> Qd;
1779 bits<4> Qd;
1945 bits<4> Qd;
2377 bits<4> Qd;
2445 bits<4> Qd;
2593 bits<4> Qd;
2666 bits<4> Qd;
2726 bits<4> Qd;
[all …]
H A DARMInstrCDE.td278 iname#"${vp}\t$coproc, $Qd, $imm", params.Cstr, params.Vpred> {
280 bits<3> Qd;
287 let Inst{15-13} = Qd{2-0};
333 iname#"${vp}\t$coproc, $Qd, $Qm, $imm", params.Cstr,
336 bits<3> Qd;
344 let Inst{15-13} = Qd{2-0};
400 iname#"${vp}\t$coproc, $Qd, $Qn, $Qm, $imm", params.Cstr,
403 bits<3> Qd;
413 let Inst{15-13} = Qd{2-0};
481 let Rd = (outs regclass:$Qd);
[all …]
H A DARMInstrNEON.td9022 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
9024 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
9026 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
9028 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
9030 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
9032 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
9034 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
9037 def : NEONInstAlias<"vcle${p}.f16 $Qd, $Qn, $Qm",
9060 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
9062 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
[all …]
H A DARMInstrFormats.td241 // instructions that both read and write their Qd register even when
262 // (which by convention will be called $Qd).
270 let vpred_constraint = ",$Qd = $vp.inactive";
/freebsd-14.2/contrib/gdtoa/
H A Dprintf.c0135 GDTOA_Qtype Qd;
991 u.Qd = va_arg(ap, GDTOA_Qtype);
1095 u.Qd = va_arg(ap, GDTOA_Qtype);
1147 u.Qd = va_arg(ap, GDTOA_Qtype);
1231 u.Qd = va_arg(ap, GDTOA_Qtype);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td484 def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
502 def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
504 def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp3797 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | in DecodeMVEModImmInstruction() local
3809 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVEModImmInstruction()
3826 unsigned Qd = fieldFromInstruction(Insn, 13, 3); in DecodeMVEVADCInstruction() local
3827 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; in DecodeMVEVADCInstruction()
3828 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVEVADCInstruction()
3842 Inst.addOperand(MCOperand::createImm(Qd)); in DecodeMVEVADCInstruction()
6724 unsigned Qd = fieldFromInstruction(Val, 13, 3); in DecodeMVE_MEM_pre() local
6730 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVE_MEM_pre()
6798 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | in DecodeMVEVMOVQtoDReg() local
6822 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | in DecodeMVEVMOVDRegtoQ() local
[all …]
/freebsd-14.2/contrib/file/tests/
H A DHWP97.hwp.testfile18 �Ü�'�7pn��D��|�>C��/C�=�B�-깴�= ��+@�a+�n69n�Ź���[HN���Qd���'M|n�;8t��e�+�{'�$^�b�!]�6�,�.V�W�…
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td787 def VMUL_N_A64 : IOpInst<"vmul_n", "..1", "Qd", OP_MUL_N>;
842 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "(<q).", "Qd">;
1063 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "..qI", "Qd", OP_MUL_LN>;
/freebsd-14.2/contrib/ncurses/include/
H A DCaps.hpux11840 exit_vertical_hl_mode rmvhlm str Qd - - ----K Exit vertical highlight mode
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7879 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); in validateInstruction() local
7882 if (Qd == Qm) { in validateInstruction()
/freebsd-14.2/contrib/netbsd-tests/usr.bin/netpgpverify/
H A Dt_netpgpverify.sh1543 wsUZ3Dem7n1B+MAfTjCN4lGlLRRlOMSrG+5n6NtMRdDx29j+g7681k8afVKyb/Qd
/freebsd-14.2/crypto/openssl/test/recipes/30-test_evp_data/
H A Devppkey_kas.txt3871 Qd+UCNkfDgId+PBSa4BjAxSV