Searched refs:QPR (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2805 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), 2889 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 5550 : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 5573 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; 5576 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; 5579 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; 5582 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; 5606 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 5619 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 6211 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2), [all …]
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| H A D | ARMRegisterInfo.td | 483 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)]; 490 // Subset of QPR that have 32-bit SPR subregs. 492 128, (trunc QPR, 8)> { 496 // Subset of QPR that have DPR_8 and SPR_8 subregs. 498 128, (trunc QPR, 4)> { 503 // parsing assembly, since we still have to truncate the register set in the QPR 506 128, (trunc QPR, 8)>; 519 128, (interleave QPR, TuplesOE2D)> { 522 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)), 523 (add (trunc QPR, 8), (trunc DPair, 16))]; [all …]
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| H A D | ARMRegisterBanks.td | 13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | A15SDOptimizer.cpp | 69 bool QPR = false); 416 unsigned Lane, bool QPR) { in createDupLane() argument 418 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane() 420 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
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