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Searched refs:PrevReg (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/cert/
H A DInvalidPtrChecker.cpp186 const MemRegion *PrevReg = *Reg; in postPreviousReturnInvalidatingCall() local
187 State = State->add<InvalidMemoryRegions>(PrevReg); in postPreviousReturnInvalidatingCall()
188 Note = C.getNoteTag([this, PrevReg, FD](PathSensitiveBugReport &BR, in postPreviousReturnInvalidatingCall()
190 if (!BR.isInteresting(PrevReg) || &BR.getBugType() != &InvalidPtrBugType) in postPreviousReturnInvalidatingCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp79 Register DstReg, Register PrevReg,
853 Register DstReg, Register PrevReg, in buildMergeLaneMasks() argument
856 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal); in buildMergeLaneMasks()
877 PrevMaskedReg = PrevReg; in buildMergeLaneMasks()
881 .addReg(PrevReg) in buildMergeLaneMasks()
H A DSILowerI1Copies.h93 Register PrevReg, Register CurReg) = 0;
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocFast.cpp989 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
990 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) { in defineLiveThroughVirtReg()
991 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
993 freePhysReg(PrevReg); in defineLiveThroughVirtReg()
999 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
1001 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
H A DModuloSchedule.cpp559 unsigned PrevReg = 0; in generateExistingPhis() local
561 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
563 NewReg, PrevReg); in generateExistingPhis()
1140 unsigned PrevReg) { in rewriteScheduledInstr() argument
1165 if (PrevReg && InProlog) in rewriteScheduledInstr()
1166 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1167 else if (PrevReg && !isLoopCarried(*Phi) && in rewriteScheduledInstr()
1169 ReplaceReg = PrevReg; in rewriteScheduledInstr()
H A DMachinePipeliner.cpp2573 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
2574 if (!PrevReg) in canUseLastOffsetValue()
2578 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg); in canUseLastOffsetValue()
2603 NewBase = PrevReg; in canUseLastOffsetValue()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h233 unsigned NewReg, unsigned PrevReg = 0);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp633 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
646 PrevReg = MCRegOp; in expandSET()
669 TmpInst.addOperand(PrevReg); in expandSET()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4388 unsigned PrevReg = FirstReg; in tryParseMatrixTileList() local
4407 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg))) in tryParseMatrixTileList()
4417 PrevReg = Reg; in tryParseMatrixTileList()
4480 int64_t PrevReg = FirstReg; in tryParseVectorList() local
4498 (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg); in tryParseVectorList()
4521 getContext().getRegisterInfo()->getEncodingValue(PrevReg); in tryParseVectorList()
4532 PrevReg = Reg; in tryParseVectorList()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1434 int PrevReg = *RegList.List->begin(); in isRegList16() local
1437 if ( Reg != PrevReg + 1) in isRegList16()
1439 PrevReg = Reg; in isRegList16()
6853 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6872 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6879 PrevReg = TmpReg; in parseRegisterList()
6886 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6897 if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6916 PrevReg = RegNo; in parseRegisterList()