| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 131 unsigned PredR = 0; member
200 unsigned PredR, bool IfTrue);
253 Register PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
334 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
709 unsigned PredR, bool IfTrue) { in predicateInstr() argument
727 MIB.addReg(PredR); in predicateInstr()
743 .addReg(PredR) in predicateInstr()
760 unsigned PredR, bool IfTrue) { in predicateBlockNB() argument
802 .addReg(PredR) in buildMux()
914 .addReg(FP.PredR) in convert()
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| H A D | HexagonGenMux.cpp | 92 unsigned PredR = 0; member
108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
250 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
257 F->second.PredR = PR; in genMuxInBlock()
338 .addReg(MX.PredR) in genMuxInBlock()
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| H A D | HexagonExpandCondsets.cpp | 225 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
232 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
769 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
792 if (RR.Reg == PredR) { in getReachingDefForPred()
932 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
940 if (!MI.readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) in renameInRange()
980 Register PredR = MP.getReg(); in predicate() local
981 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
998 if (!MI.modifiesRegister(PredR, nullptr)) in predicate()
1010 if (PredValid && HII->isPredicated(MI) && MI.readsRegister(PredR)) in predicate()
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| H A D | HexagonHardwareLoops.cpp | 464 Register PredR; in findInductionRegister() local
466 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
469 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1334 Register PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1342 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1897 Register PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1903 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| H A D | HexagonISelLowering.cpp | 378 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
379 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 276 if (!ICmpInst::isEquality(PredR)) in getMaskedTypeForICmpPair()
354 if (PredR != NewCC) in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
468 PredL, PredR, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
474 PredR, PredL, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
1323 !matchUnorderedInfCompare(PredR, RHS0, RHS1)) in matchIsFiniteTest()
1342 PredR = FCmpInst::getSwappedPredicate(PredR); in foldLogicOfFCmps()
1362 unsigned FCmpCodeR = getFCmpCode(PredR); in foldLogicOfFCmps()
3166 if (predicatesFoldable(PredL, PredR)) { in foldAndOrOfICmps()
3312 isSignBitCheck(PredR, *RHSC, TrueIfSignedR) && in foldAndOrOfICmps()
3979 if (predicatesFoldable(PredL, PredR)) { in foldXorOfICmps()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanRecipes.cpp | 1437 if (auto *PredR = dyn_cast<VPPredInstPHIRecipe>(U)) in shouldPack() local
1438 return any_of(PredR->users(), [PredR](const VPUser *U) { in shouldPack()
1439 return !U->usesScalars(PredR); in shouldPack()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 454 CmpInst::Predicate PredL, PredR; in isEqualImpl() local
457 match(CondR, m_Cmp(PredR, m_Specific(X), m_Specific(Y))) && in isEqualImpl()
458 CmpInst::getInversePredicate(PredL) == PredR) in isEqualImpl()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1859 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
1860 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) || in simplifyAndOrOfFCmps()
1861 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) { in simplifyAndOrOfFCmps()
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