| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 139 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad() 182 LD->getAddressingMode() != ISD::POST_INC) in selectIndexedProgMemLoad()
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| H A D | AVRISelLowering.cpp | 123 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering() 124 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering() 127 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering() 128 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering() 1194 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1455 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
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| H A D | BasicTTIImpl.h | 200 return ISD::POST_INC; in getISDIndexedMode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelDAGToDAG.cpp | 304 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| H A D | MSP430ISelLowering.cpp | 61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering() 62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering() 1357 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 836 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg() 872 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre() 892 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm() 971 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset() 1089 if (AM != ISD::POST_INC) in SelectAddrMode6Offset() 1400 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset() 1469 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset() 1672 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD || in tryT1IndexedLoad()
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| H A D | ARMISelLowering.cpp | 1131 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering() 1132 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering() 20015 AM = ISD::POST_INC; in getPostIndexedAddressParts() 20049 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| H A D | ARMInstrMVE.td | 7122 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 7216 …return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::POST_INC || AM == ISD::POST_…
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 530 case ISD::POST_INC: return "<post-inc>"; in getIndexedModeName()
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| H A D | DAGCombiner.cpp | 18357 if (getCombineLoadStoreParts(Use, ISD::POST_INC, ISD::POST_DEC, IsLoad, in shouldCombineToPostInc() 18383 if (!getCombineLoadStoreParts(N, ISD::POST_INC, ISD::POST_DEC, IsLoad, in getPostIndexedLoadStoreOp() 18486 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 650 AM = ISD::POST_INC; in getPostIndexedAddressParts() 1801 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering() 1802 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 193 setIndexedLoadAction(ISD::POST_INC, T, Legal); in initializeHVXLowering() 194 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 766 assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) && in tryIndexedLoad() 769 bool IsPost = AM == ISD::POST_INC; in tryIndexedLoad()
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| H A D | RISCVISelLowering.cpp | 1355 for (unsigned im : {ISD::PRE_INC, ISD::POST_INC}) { in RISCVTargetLowering() 19650 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 1332 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1338 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 24327 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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