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Searched refs:PLL_BASE_ENABLE (Results 1 – 2 of 2) sorted by relevance

/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c68 #define PLL_BASE_ENABLE (1 << 30) macro
421 reg |= PLL_BASE_ENABLE; in pll_enable()
434 reg &= ~PLL_BASE_ENABLE; in pll_disable()
696 *enabled = reg & PLL_BASE_ENABLE ? true: false; in tegra124_pll_get_gate()
742 reg |= PLL_BASE_ENABLE; in pll_set_std()
754 reg &= ~PLL_BASE_ENABLE; in pll_set_std()
916 reg &= ~PLL_BASE_ENABLE; in pllx_set_freq()
936 reg |= PLL_BASE_ENABLE; in pllx_set_freq()
943 reg &= ~PLL_BASE_ENABLE; in pllx_set_freq()
1007 if (reg & PLL_BASE_ENABLE) { in tegra124_pll_init()
/freebsd-14.2/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c79 #define PLL_BASE_ENABLE (1 << 30) macro
607 reg |= PLL_BASE_ENABLE; in pll_enable()
620 reg &= ~PLL_BASE_ENABLE; in pll_disable()
894 *enabled = reg & PLL_BASE_ENABLE ? true: false; in tegra210_pll_get_gate()
940 reg |= PLL_BASE_ENABLE; in pll_set_std()
952 reg &= ~PLL_BASE_ENABLE; in pll_set_std()
1318 if (reg & PLL_BASE_ENABLE) { in tegra210_pll_init()