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Searched refs:PLLE_SS_CNTL (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c587 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
589 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
603 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
608 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
611 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
615 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra124_car.h54 #define PLLE_SS_CNTL 0x068 macro
/freebsd-14.2/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c780 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
782 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
794 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
803 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
806 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
810 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
H A Dtegra210_car.h58 #define PLLE_SS_CNTL 0x068 macro