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Searched refs:PLL4 (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-ipq8064.yaml34 - description: PLL4 from LCC
64 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-audio.yaml19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
H A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/freebsd-14.2/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
H A Dqcom,lcc-mdm9615.h11 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
H A Dstm32mp13-clks.h22 #define PLL4 9 macro
H A Dstm32mp1-clks.h186 #define PLL4 179 macro
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dstm32mp157c-odyssey.dts41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
H A Dqcom-msm8960.dtsi136 <&lcc PLL4>;
H A Dqcom-ipq8064.dtsi517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
H A Dqcom-apq8064.dtsi837 <&lcc PLL4>;
/freebsd-14.2/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_attach.c3375 #define PLL4 0x1618c macro
3386 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9300_get_pll3_sqsum_dvc()
/freebsd-14.2/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-main.dtsi1045 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via