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Searched refs:PLL (Results 1 – 25 of 215) sorted by relevance

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/freebsd-14.2/sys/arm64/qoriq/clk/
H A Dlx2160a_clkgen.c49 #define PLL(_id1, _id2, cname, o, d) \ macro
67 PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);
69 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);
71 PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);
73 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);
75 PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);
87 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cg_divs)},
89 {PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cg_divs)},
91 {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cg_divs)},
93 {PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cg_divs)},
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,mmcc.yaml83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
89 - description: HDMI phy PLL clock
121 - description: HDMI phy PLL clock
160 - description: HDMI phy PLL clock
204 - description: Global PLL 0 clock
211 - description: HDMI phy PLL clock
235 - description: Global PLL 0 clock
241 - description: HDMI phy PLL clock
264 - description: Global PLL 0 clock
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H A Dqcom,a53pll.yaml7 title: Qualcomm A53 PLL clock
13 The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
49 # Example 1 - A53 PLL found on MSM8916 devices
56 # Example 2 - A53 PLL found on IPQ6018 devices
H A Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
89 PLL and leaf clock compatible strings for Cygnus are:
97 The following table defines the set of PLL/clock index and ID for Cygnus.
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
186 PLL and leaf clock compatible strings for Northstar 2 are:
234 PLL and leaf clock compatible strings for BCM63138 are:
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H A Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
H A Dbaikal,bt1-ccu-pll.yaml8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
113 # Clock Control Unit PLL node:
H A Dti,cdce925.yaml15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
54 "^PLL[1-4]$":
97 /* PLL options to get SSC 1% centered */
H A Ddove-divider-clock.txt1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
H A Dti,cdce925.txt16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
48 /* PLL options to get SSC 1% centered */
H A Dfsl,plldig.yaml14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
32 of this PLL cannot be changed during runtime only at startup. Therefore,
35 its own desired VCO frequency for the PLL.
H A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
H A Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
H A Dallwinner,sun6i-a31-pll6-clk.yaml7 title: Allwinner A31 Peripheral PLL
19 The first output is the regular PLL output, the second is a PLL
H A Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
H A Dqcom,dispcc-sc8280xp.yaml38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
40 - description: DSI 1 PLL byte clock
41 - description: DSI 1 PLL DSI clock
H A Dallwinner,sun4i-a10-pll6-clk.yaml7 title: Allwinner A10 Peripheral PLL
20 regular PLL output, the third is a PLL output at twice the rate.
H A Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
70 platform PLL.
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
132 * 0 - equal to the PLL frequency
133 * 1 - equal to the PLL frequency divided by 2
134 * 2 - equal to the PLL frequency divided by 4
H A Dbaikal,bt1-ccu-div.yaml96 - description: CCU SATA PLL output clock
97 - description: CCU PCIe PLL output clock
98 - description: CCU Ethernet PLL output clock
111 - description: CCU SATA PLL output clock
112 - description: CCU PCIe PLL output clock
113 - description: CCU Ethernet PLL output clock
182 # Required Clock Control Unit PLL node:
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Dtas2552.txt19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
22 defined values to select and configure the PLL and PDM reference clocks.
/freebsd-14.2/sys/contrib/device-tree/Bindings/phy/
H A Dphy-stm32-usbphyc.txt6 PLL configuration.
9 |_ PLL
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
/freebsd-14.2/sys/riscv/sifive/
H A Dsifive_prci.c112 #define PLL(_id, _name, _base) \ macro
119 #define PLL_END PLL(0, NULL, 0)
178 PLL(FU540_PRCI_CORECLK, "coreclk", FU540_PRCI_COREPLL_CFG0),
179 PLL(FU540_PRCI_DDRCLK, "ddrclk", FU540_PRCI_DDRPLL_CFG0),
180 PLL(FU540_PRCI_GEMGXLCLK, "gemgxlclk", FU540_PRCI_GEMGXLPLL_CFG0),
225 PLL(FU740_PRCI_CORECLK, "coreclk", FU740_PRCI_COREPLL_CFG0),
226 PLL(FU740_PRCI_DDRCLK, "ddrclk", FU740_PRCI_DDRPLL_CFG0),
227 PLL(FU740_PRCI_GEMGXLCLK, "gemgxlclk", FU740_PRCI_GEMGXLPLL_CFG0),
228 PLL(FU740_PRCI_DVFSCORECLK, "dvfscoreclk", FU740_PRCI_DVFSCOREPLL_CFG0),
229 PLL(FU740_PRCI_HFPCLK, "hfpclk", FU740_PRCI_HFPCLKPLL_CFG0),
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/freebsd-14.2/sys/contrib/device-tree/Bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
/freebsd-14.2/sys/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt1 C6X PLL Clock Controllers
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c117 #define PLL(_id, cname, pname) \ macro
219 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
230 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
243 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
301 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
311 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
322 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
332 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
345 PLL(0, "pllREFE_out", "osc_div_clk"),
358 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
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