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Searched refs:PCIE (Results 1 – 25 of 79) sorted by relevance

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/freebsd-14.2/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mt7622-pcie-mirror.yaml7 title: MediaTek PCIE Mirror Controller for MT7622
14 The mediatek PCIE mirror provides a configuration interface for PCIE
H A Dmediatek,mt7986-wed-pcie.yaml7 title: MediaTek PCIE WED Controller for MT7986
14 The mediatek WED PCIE provides a configuration interface for PCIE
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,ipq5332-gcc.yaml29 - description: PCIE 2lane PHY pipe clock source
30 - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
31 - description: USB PCIE wrapper pipe clock source
H A Dqcom,sm8550-gcc.yaml26 - description: PCIE 0 Pipe clock source
27 - description: PCIE 1 Pipe clock source
28 - description: PCIE 1 Phy Auxiliary clock source
H A Dqcom,gcc-sm8450.yaml26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
28 - description: PCIE 1 Phy Auxillary clock source (Optional clock)
H A Dqcom,qdu1000-gcc.yaml26 - description: PCIE 0 Pipe clock source
27 - description: PCIE 0 Phy Auxiliary clock source
H A Dqcom,gcc-sc7280.yaml27 - description: PCIE-0 pipe clock source
28 - description: PCIE-1 pipe clock source
H A Dqcom,gcc-sdm845.yaml71 - description: PCIE 0 Pipe clock source
72 - description: PCIE 1 Pipe clock source
H A Dqcom,gcc-sm8350.yaml26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
H A Dqcom,gcc-sdx65.yaml27 - description: PCIE Pipe clock source
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmarvell-8xxx.txt1 Marvell 8787/8897/8978/8997 (sd8787/sd8897/sd8978/sd8997/pcie8997) SDIO/PCIE devices
4 This node provides properties for controlling the Marvell SDIO/PCIE wireless device.
5 The node is expected to be specified as a child node to the SDIO/PCIE controller that
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dimx6qdl-mba6.dtsi94 /* PCIE.PWR_EN */
438 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
439 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
440 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
468 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
H A Daspeed-bmc-tyan-s7106.dts360 * - 0,0: PCIE slot 1, SMB #1
361 * - 0,1: PCIE slot 1, SMB #2
362 * - 1,0: PCIE slot 2, SMB #1
363 * - 1,1: PCIE slot 2, SMB #2
/freebsd-14.2/sys/contrib/device-tree/Bindings/phy/
H A Dxlnx,zynqmp-psgtr.yaml14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
36 maximum: 3 # for PCIE or SGMII
H A Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
H A Damlogic,meson-axg-pcie.yaml7 title: Amlogic AXG PCIE PHY
H A Damlogic,meson-g12a-usb3-pcie-phy.yaml8 title: Amlogic G12A USB3 + PCIE Combo PHY
H A Damlogic,meson-axg-mipi-pcie-analog.yaml7 title: Amlogic AXG shared MIPI/PCIE analog PHY
H A Damlogic,g12a-usb3-pcie-phy.yaml8 title: Amlogic G12A USB3 + PCIE Combo PHY
/freebsd-14.2/sys/contrib/device-tree/Bindings/pci/
H A Damlogic,meson-pcie.txt1 Amlogic Meson AXG DWC PCIE SoC controller
32 - phys: should contain a phandle to the PCIE phy
/freebsd-14.2/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zcu102-revA.dts239 output-low; /* PCIE = 0, DP = 1 */
245 output-high; /* PCIE = 0, DP = 1 */
251 output-high; /* PCIE = 0, USB0 = 1 */
257 output-high; /* PCIE = 0, SATA = 1 */
545 /* refclk4 for PS-GT, used for PCIE slot */
550 /* refclk5 for PS-GT, used for PCIE */
/freebsd-14.2/sys/dev/bhnd/cores/pci/
H A Dbhnd_pci.c81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
/freebsd-14.2/sys/contrib/dev/athk/ath11k/
H A DKconfig28 This module adds support for PCIE bus
/freebsd-14.2/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,nsp.yaml14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
/freebsd-14.2/sys/contrib/device-tree/src/arm64/renesas/
H A Dsalvator-xs.dtsi37 line-name = "PCIE/SATA switch";

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