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Searched refs:PCI (Results 1 – 25 of 271) sorted by relevance

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/freebsd-14.2/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8641_hpcn_36b.dts134 /* IDSEL 0x11 func 0 - PCI slot 1 */
140 /* IDSEL 0x11 func 1 - PCI slot 1 */
146 /* IDSEL 0x11 func 2 - PCI slot 1 */
152 /* IDSEL 0x11 func 3 - PCI slot 1 */
158 /* IDSEL 0x11 func 4 - PCI slot 1 */
164 /* IDSEL 0x11 func 5 - PCI slot 1 */
170 /* IDSEL 0x11 func 6 - PCI slot 1 */
176 /* IDSEL 0x11 func 7 - PCI slot 1 */
182 /* IDSEL 0x12 func 0 - PCI slot 2 */
188 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
H A Dmpc8641_hpcn.dts167 /* IDSEL 0x11 func 0 - PCI slot 1 */
173 /* IDSEL 0x11 func 1 - PCI slot 1 */
179 /* IDSEL 0x11 func 2 - PCI slot 1 */
185 /* IDSEL 0x11 func 3 - PCI slot 1 */
191 /* IDSEL 0x11 func 4 - PCI slot 1 */
197 /* IDSEL 0x11 func 5 - PCI slot 1 */
203 /* IDSEL 0x11 func 6 - PCI slot 1 */
209 /* IDSEL 0x11 func 7 - PCI slot 1 */
215 /* IDSEL 0x12 func 0 - PCI slot 2 */
221 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
H A Dmpc8572ds.dtsi249 /* IDSEL 0x11 func 0 - PCI slot 1 */
255 /* IDSEL 0x11 func 1 - PCI slot 1 */
261 /* IDSEL 0x11 func 2 - PCI slot 1 */
267 /* IDSEL 0x11 func 3 - PCI slot 1 */
273 /* IDSEL 0x11 func 4 - PCI slot 1 */
279 /* IDSEL 0x11 func 5 - PCI slot 1 */
285 /* IDSEL 0x11 func 6 - PCI slot 1 */
291 /* IDSEL 0x11 func 7 - PCI slot 1 */
297 /* IDSEL 0x12 func 0 - PCI slot 2 */
303 /* IDSEL 0x12 func 1 - PCI slot 2 */
[all …]
H A Dp2020ds.dtsi219 // IDSEL 0x11 func 0 - PCI slot 1
223 // IDSEL 0x11 func 1 - PCI slot 1
227 // IDSEL 0x11 func 2 - PCI slot 1
231 // IDSEL 0x11 func 3 - PCI slot 1
235 // IDSEL 0x11 func 4 - PCI slot 1
239 // IDSEL 0x11 func 5 - PCI slot 1
243 // IDSEL 0x11 func 6 - PCI slot 1
247 // IDSEL 0x11 func 7 - PCI slot 1
/freebsd-14.2/share/misc/
H A Dpci_vendors41 7a09 PCI-to-PCI Bridge
49 7a19 PCI-to-PCI Bridge
53 7a29 PCI-to-PCI Bridge
81 0002 Propolis PCI-PCI Bridge
4090 7915 RS690 PCI to PCI Bridge (PCI Express Port 1)
4091 7916 RS690 PCI to PCI Bridge (PCI Express Port 2)
4092 7917 RS690 PCI to PCI Bridge (PCI Express Port 3)
4105 7935 RS600 PCI to PCI Bridge (PCI Express Port 1)
6313 0125 uPD720400 PCI Express - PCI/PCI-X Bridge
9232 8114 PEX 8114 PCI Express-to-PCI/PCI-X Bridge
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqca,ath9k.txt4 node is expected to be specified as a child node of the PCI controller to
8 - compatible: For PCI and PCIe devices this should be an identifier following
9 the format as defined in "PCI Bus Binding to Open Firmware"
11 where VVVV is the PCI vendor ID and DDDD is PCI device ID.
12 Typically QCA's PCI vendor ID 168c is used while the PCI device
41 In this example, the node is defined as child node of the PCI controller:
/freebsd-14.2/sys/contrib/device-tree/Bindings/pci/
H A Dralink,rt3883-pci.txt1 * Mediatek/Ralink RT3883 PCI controller
29 interrupt controller and the PCI host bridge.
48 b) PCI host bridge:
63 - bus-range: PCI bus numbers covered
65 - ranges: specifies the ranges for the PCI memory and I/O regions
68 - interrupt-map: standard PCI properties to define the mapping of the
69 PCI interface to interrupt numbers.
71 The PCI host bridge node might have additional sub-nodes representing
72 the onboard PCI devices/PCI slots. Each such sub-node must have the
80 If a given sub-node represents a PCI bridge it must have following
[all …]
H A Dfaraday,ftpci100.txt1 Faraday Technology FTPCI100 PCI Host Bridge
3 This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
5 plain and dual PCI. The plain version embeds a cascading interrupt controller
9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
35 PCI clock (PCICLK). If these are not present, they are assumed to be
36 hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
38 clock and "PCICLK" for the PCI-side clock.
88 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
89 <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
90 <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
[all …]
H A D83xx-512x-pci.txt1 * Freescale 83xx and 512x PCI bridges
3 Freescale 83xx and 512x SOCs include the same PCI bridge core.
7 The first is for the internal PCI bridge registers
8 The second is for the PCI config space access registers
14 /* IDSEL 0x0E -mini PCI */
20 /* IDSEL 0x0F - PCI slot */
H A Dfsl,pci.txt1 * Bus Enumeration by Freescale PCI-X Agent
3 Typically any Freescale PCI-X bridge hardware strapped into Agent mode
5 all mezzanines to be PCI-X Agents, but one per system may still
8 The property defined below will allow a PCI-X bridge to be used for bus
17 /* PCI-X bridge known to be PrPMC Monarch */
H A Dpci-keystone.txt3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
31 PCI in either RC mode or EP mode.
63 phys: phandle to generic Keystone SerDes PHY for PCI
64 phy-names: name of the generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
69 DesignWare DT Properties not applicable for Keystone PCI
93 PCI in either RC mode or EP mode.
H A Dintel,ixp4xx-pci.yaml7 title: Intel IXP4xx PCI controller
12 description: PCI host controller found in the Intel IXP4xx SoC series.
32 - description: Main PCI interrupt
33 - description: PCI DMA interrupt 1
34 - description: PCI DMA interrupt 2
43 description: The DMA range tells the PCI host which addresses
H A Dpci.txt1 PCI bus bridges have standardized Device Tree bindings:
3 PCI Bus Binding to: IEEE Std 1275-1994
15 If present this property assigns a fixed PCI domain number to a host bridge,
22 If present this property specifies PCI gen for link capability. Host
36 PCI-PCI Bridge properties
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
H A Dmobiveil-pcie.txt27 - bus-range: PCI bus numbers covered
35 interrupt-map: standard PCI properties to define the mapping of the
36 PCI interface to interrupt numbers.
37 - ranges: ranges for the PCI memory regions (I/O space region is not
39 Please refer to the standard PCI bus binding document for a more
H A Dxilinx-pcie.txt13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
15 - ranges: ranges for the PCI memory regions (I/O space region is not
17 Please refer to the standard PCI bus binding document for a more
21 - bus-range: PCI bus numbers covered
H A Dfaraday,ftpci100.yaml7 title: Faraday Technology FTPCI100 PCI Host Bridge
13 This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
15 plain and dual PCI. The plain version embeds a cascading interrupt controller
18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
29 The code which is the only documentation of how the Faraday PCI (the non-dual
91 - description: PCI clock (PCICLK).
94 hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
H A Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
29 PCI root complex
/freebsd-14.2/sys/contrib/dev/rtw89/
H A DKconfig32 tristate "Realtek 8851BE PCI wireless network (Wi-Fi 6) adapter"
33 depends on PCI
43 tristate "Realtek 8852AE PCI wireless network (Wi-Fi 6) adapter"
44 depends on PCI
54 tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
55 depends on PCI
65 tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter"
66 depends on PCI
/freebsd-14.2/sys/contrib/device-tree/Bindings/virtio/
H A Diommu.txt1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
4 discovered dynamically by the PCI probing infrastructure. However the
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
42 * The IOMMU manages all functions in this PCI domain except
H A Dpci-iommu.yaml13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
25 # according to the PCI Bus Binding specification. Since PCI provides
37 PCI address of the IOMMU. As defined in the PCI Bus Binding
67 * The IOMMU manages all functions in this PCI domain except
/freebsd-14.2/contrib/file/magic/Magdir/
H A Dpci_ids4 # pci.ids: file(1) magic for PCI specific informations
8 # show hexadecimal PCI vendor identification in human readable text form
9 0 name PCI-vendor
43 # Base class code https://wiki.osdev.org/PCI
44 # show hexadecimal PCI class+sub+ProgIF identification in human readable text form
45 0 name PCI-class
114 # Prog IF of PCI class code?
/freebsd-14.2/sys/arm64/conf/
H A Dstd.virt14 # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure
19 device virtio_pci # VirtIO PCI device
/freebsd-14.2/sys/dev/pci/
H A Dpcib_if.m55 # Return the number of slots on the attached PCI bus.
63 # Return the number of functions on the attached PCI bus.
70 # Read configuration space on the PCI bus. The bus, slot and func
86 # Write configuration space on the PCI bus. The bus, slot and func
179 # Return the PCI Routing Identifier (RID) for the device.
198 # Return non-zero if PCI ARI is enabled, or zero otherwise
205 # Decode a PCI Routing Identifier (RID) into PCI bus/slot/function
216 # Request control of PCI features from host firmware, if any.
/freebsd-14.2/sys/contrib/device-tree/Bindings/x86/
H A Dce4100.txt47 The PCI node
49 This node describes the PCI bus on the SoC. Its property should be
56 to contain at least the reg property containing the PCI bus address and
57 compatible property according to "PCI Bus Binding Revision 2.1".
/freebsd-14.2/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-pxa-pci-ce4100.txt4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar

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