Home
last modified time | relevance | path

Searched refs:Outputs (Results 1 – 25 of 38) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp335 return rr0(RC, Outputs); in evaluate()
351 return rr0(RC, Outputs); in evaluate()
373 return rr0(RC, Outputs); in evaluate()
382 return rr0(RC, Outputs); in evaluate()
386 return rr0(RC, Outputs); in evaluate()
390 return rr0(RC, Outputs); in evaluate()
395 return rr0(RC, Outputs); in evaluate()
400 return rr0(RC, Outputs); in evaluate()
405 return rr0(RC, Outputs); in evaluate()
1212 putCell(RD, Res, Outputs); in evaluateLoad()
[all …]
H A DHexagonBitTracker.h35 CellMapType &Outputs) const override;
53 CellMapType &Outputs) const;
55 CellMapType &Outputs) const;
H A DHexagonConstPropagation.cpp687 CellMap Outputs; in visitNonBranch() local
692 for (auto &I : Outputs) in visitNonBranch()
716 if (!Outputs.has(DefR.Reg)) in visitNonBranch()
1864 CellMap &Outputs);
1869 CellMap &Outputs);
1871 CellMap &Outputs);
1873 CellMap &Outputs);
1875 CellMap &Outputs);
1877 CellMap &Outputs);
2757 Outputs.update(DefR.Reg, RC); in evaluateHexExt()
[all …]
/freebsd-14.2/crypto/openssl/doc/man1/
H A Dopenssl-info.pod.in40 Outputs the default directory for OpenSSL configuration files.
44 Outputs the default directory for OpenSSL engine modules.
48 Outputs the default directory for OpenSSL dynamically loadable modules
53 Outputs the DSO extension OpenSSL uses.
57 Outputs the separator character between a directory specification and
64 Outputs the OpenSSL list separator character.
70 Outputs the randomness seed sources.
74 Outputs the OpenSSL CPU settings info.
H A Dopenssl-crl.pod.in120 Outputs the "hash" of the CRL issuer name using the older algorithm
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/
H A DTool.cpp21 const InputInfoList &Outputs, in ConstructJobMultipleOutputs() argument
25 assert(Outputs.size() == 1 && "Expected only one output by default!"); in ConstructJobMultipleOutputs()
26 ConstructJob(C, JA, Outputs.front(), Inputs, TCArgs, LinkingOutput); in ConstructJobMultipleOutputs()
H A DJob.cpp42 ArrayRef<InputInfo> Inputs, ArrayRef<InputInfo> Outputs, in Command() argument
49 for (const auto &II : Outputs) in Command()
396 ArrayRef<InputInfo> Inputs, ArrayRef<InputInfo> Outputs, in CC1Command() argument
399 Outputs, PrependArg) { in CC1Command()
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.txt16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
H A Dti,cdce925.yaml15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
H A Dnvidia,tegra20-car.yaml23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dnvidia,tegra124-car.yaml23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DTFLiteUtils.cpp41 EvaluationResultImpl(const std::vector<const TfLiteTensor *> &Outputs) in EvaluationResultImpl() argument
42 : Outputs(Outputs){}; in EvaluationResultImpl()
44 const TfLiteTensor *getOutput(size_t I) { return Outputs[I]; } in getOutput()
50 const std::vector<const TfLiteTensor *> Outputs; member in llvm::EvaluationResultImpl
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DCodeExtractor.h174 ValueSet &Inputs, ValueSet &Outputs);
200 void findInputsOutputs(ValueSet &Inputs, ValueSet &Outputs,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DIROutliner.cpp898 CE->findInputsOutputs(PremappedInputs, Outputs, SinkCands); in getCodeExtractorArguments()
1120 Outputs.insert(&PN); in analyzeExitPHIsForOutputUses()
1315 for (Value *Output : Outputs) { in findExtractedOutputToOverallOutputMapping()
1403 SetVector<Value *> ArgInputs, Outputs; in findAddInputsOutputs() local
1406 Outputs); in findAddInputsOutputs()
2696 if (!OutputMappings.contains(Outputs[*OutputIdx])) { in updateOutputMapping()
2698 << *Outputs[*OutputIdx] << "\n"); in updateOutputMapping()
2703 << *Outputs[*OutputIdx] << "\n"); in updateOutputMapping()
2709 SetVector<Value *> ArgInputs, Outputs, SinkCands; in extractSection() local
2715 Region.CE->extractCodeRegion(CEAC, ArgInputs, Outputs); in extractSection()
[all …]
H A DHotColdSplitting.cpp389 SetVector<Value *> Inputs, Outputs, Sinks; in extractColdRegion() local
390 CE.findInputsOutputs(Inputs, Outputs, Sinks); in extractColdRegion()
393 getOutliningPenalty(Region, Inputs.size(), Outputs.size()); in extractColdRegion()
H A DPartialInlining.cpp1108 SetVector<Value *> Inputs, Outputs, Sinks; in doMultiRegionFunctionOutlining() local
1119 CE.findInputsOutputs(Inputs, Outputs, Sinks); in doMultiRegionFunctionOutlining()
1123 dbgs() << "outputs: " << Outputs.size() << "\n"; in doMultiRegionFunctionOutlining()
1126 for (Value *output : Outputs) in doMultiRegionFunctionOutlining()
1131 if (Outputs.size() > 0 && !ForceLiveExit) in doMultiRegionFunctionOutlining()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Driver/
H A DJob.h175 ArrayRef<InputInfo> Outputs = std::nullopt,
249 ArrayRef<InputInfo> Outputs = std::nullopt,
H A DTool.h88 const InputInfoList &Outputs,
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DIROutliner.h294 ArrayRef<Value *> Outputs, LoadInst *LI);
/freebsd-14.2/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,sci-intr.yaml23 | Inputs Outputs |
H A Dbrcm,bcm7120-l2-intc.txt24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
H A Dti,sci-intr.txt11 | Inputs Outputs |
H A Dbrcm,bcm7120-l2-intc.yaml34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
/freebsd-14.2/share/examples/BSD_daemon/
H A DREADME64 An example of how to use the stuff above. Outputs a simple
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DClang.h156 const InputInfoList &Outputs,

12