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Searched refs:OutVT (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp416 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
5533 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SPLICE() local
5553 EVT OutVT = N->getValueType(0); in PromoteIntRes_EXTRACT_SUBVECTOR() local
5563 if (OutVT.isScalableVector()) { in PromoteIntRes_EXTRACT_SUBVECTOR()
5607 if (OutVT.isScalableVector()) in PromoteIntRes_EXTRACT_SUBVECTOR()
5636 EVT OutVT = N->getValueType(0); in PromoteIntRes_INSERT_SUBVECTOR() local
5660 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_REVERSE() local
5674 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SHUFFLE() local
5680 EVT OutVT = N->getValueType(0); in PromoteIntRes_BUILD_VECTOR() local
5720 EVT OutVT = N->getValueType(0); in PromoteIntRes_ScalarOp() local
[all …]
H A DLegalizeVectorTypes.cpp3225 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
3247 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
3248 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
3833 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
3834 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
3835 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
3838 unsigned OutElementSize = OutVT.getScalarSizeInBits(); in SplitVecOp_TruncateHelper()
3842 std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT); in SplitVecOp_TruncateHelper()
3903 ISD::STRICT_FP_ROUND, DL, {OutVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3912 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
[all …]
H A DSelectionDAGBuilder.cpp11918 EVT OutVT = in visitVectorDeinterleave() local
11921 unsigned OutNumElts = OutVT.getVectorMinNumElements(); in visitVectorDeinterleave()
11924 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
11926 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
11931 if (OutVT.isFixedLengthVector()) { in visitVectorDeinterleave()
11932 SDValue Even = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, in visitVectorDeinterleave()
11934 SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, in visitVectorDeinterleave()
11942 DAG.getVTList(OutVT, OutVT), Lo, Hi); in visitVectorDeinterleave()
11952 EVT OutVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitVectorInterleave() local
11956 if (OutVT.isFixedLengthVector()) { in visitVectorInterleave()
[all …]
H A DDAGCombiner.cpp634 std::optional<EVT> OutVT = std::nullopt);
24834 if ((LegalTypes && !TLI.isTypeLegal(OutVT)) || in canCombineShuffleToExtendVectorInreg()
24839 return OutVT; in canCombineShuffleToExtendVectorInreg()
24876 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToAnyExtendVectorInreg() local
24878 if (!OutVT) in combineShuffleToAnyExtendVectorInreg()
24880 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0)); in combineShuffleToAnyExtendVectorInreg()
24997 std::optional<EVT> OutVT = canCombineShuffleToExtendVectorInreg( in combineShuffleToZeroExtendVectorInReg() local
25000 if (OutVT) in combineShuffleToZeroExtendVectorInReg()
25001 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, in combineShuffleToZeroExtendVectorInReg()
27638 std::optional<EVT> OutVT) { in BuildLogBase2() argument
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2728 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2731 OutVT = MVT::i16; in truncateVectorWithNARROW()
2735 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithNARROW()
2745 SDValue Res = DAG.getNode(WebAssemblyISD::NARROW_U, DL, OutVT, Lo, Hi); in truncateVectorWithNARROW()
2768 EVT OutVT = N->getValueType(0); in performTruncateCombine() local
2769 if (!OutVT.isVector()) in performTruncateCombine()
2772 EVT OutSVT = OutVT.getVectorElementType(); in performTruncateCombine()
2776 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
2781 OutVT.getScalarSizeInBits()); in performTruncateCombine()
2783 return truncateVectorWithNARROW(OutVT, In, DL, DAG); in performTruncateCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5180 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
5558 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
5960 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5962 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5966 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), in lowerSIGN_EXTEND_VECTOR_INREG() local
5979 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5982 unsigned OutNumElts = OutVT.getVectorNumElements(); in lowerZERO_EXTEND_VECTOR_INREG()
5998 return DAG.getNode(ISD::BITCAST, DL, OutVT, Shuf); in lowerZERO_EXTEND_VECTOR_INREG()
7304 EVT OutVT = N->getValueType(0); in combineINT_TO_FP() local
7305 Type *OutLLVMTy = OutVT.getTypeForEVT(Ctx); in combineINT_TO_FP()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSSE.td3771 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3782 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3791 (OutVT (OpNode (ArgVT RC:$src1),
3796 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3807 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3816 (OutVT (OpNode (ArgVT RC:$src1),
H A DX86ISelLowering.cpp20144 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
20148 OutVT = MVT::i16; in truncateVectorWithPACK()
20155 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20159 SDValue Res = DAG.getNode(Opcode, DL, OutVT, LHS, RHS); in truncateVectorWithPACK()
20179 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20185 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20194 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20200 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
20202 Res = DAG.getVectorShuffle(OutVT, DL, Res, Res, Mask); in truncateVectorWithPACK()
H A DX86InstrAVX512.td161 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
166 AVX512_maskable_common<O, F, OutVT, Outs,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td2801 ValueType OutVT, ValueType InVT,
2804 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2837 multiclass sve2_fp_mla_long<bits<3> opc, string asm, ValueType OutVT,
2840 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
H A DAArch64ISelLowering.cpp19850 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
19851 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
19852 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
19872 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
23261 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
23263 OutVT = DAG.getValueType(HwRetVt); in performGatherLoadCombine()
23268 Base, Offset, OutVT}; in performGatherLoadCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8658 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8659 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()