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Searched refs:OrigReg (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp219 Register OrigReg, MachineOperand *RowMO, in reload() argument
221 int FI = getStackSpaceFor(OrigReg); in reload()
222 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
261 if (MO.isReg() && MO.getReg() == OrigReg) in reload()
267 LLVM_DEBUG(dbgs() << "Reloading " << printReg(OrigReg, TRI) << " into " in reload()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp554 Register OrigReg = U.getReg(); in colorChain() local
555 U.setReg(Substs[OrigReg]); in colorChain()
559 ToErase.push_back(OrigReg); in colorChain()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTailDuplicator.h101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTailDuplicator.cpp331 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg, in addSSAUpdateEntry() argument
334 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
340 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
341 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
H A DRegisterBankInfo.cpp472 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
474 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
480 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
H A DInlineSpiller.cpp1358 Register OrigReg = OrigLI.reg(); in isSpillCandBB() local
1359 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
H A DSplitKit.cpp336 Register OrigReg = VRM.getOriginal(CurLI->reg()); in isOriginalEndpoint() local
337 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp680 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments() local
683 BoolArgs.push_back({OrigReg, WideReg}); in lowerFormalArguments()
710 Register OrigReg = KV.first; in lowerFormalArguments() local
713 assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 && in lowerFormalArguments()
716 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0)); in lowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp4234 const SCEV *OrigReg; member
4237 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4247 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4296 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4301 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4329 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4344 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4346 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
4359 if (F.ScaledReg == OrigReg) { in GenerateCrossUseConstantOffsets()
4388 if (BaseReg != OrigReg) in GenerateCrossUseConstantOffsets()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1685 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1691 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1696 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1698 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1700 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1710 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()