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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVUtils.h70 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord);
H A DSPIRVUtils.cpp192 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) { in getMemSemantics() argument
193 switch (Ord) { in getMemSemantics()
H A DSPIRVInstructionSelector.cpp558 static SPIRV::Scope::Scope getScope(SyncScope::ID Ord) { in getScope() argument
559 switch (Ord) { in getScope()
713 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); in selectFence() local
714 uint32_t Scope = static_cast<uint32_t>(getScope(Ord)); in selectFence()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp61 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) : in FrameRef() argument
62 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
H A DTargetLoweringBase.cpp2357 AtomicOrdering Ord) const { in emitLeadingFence()
2358 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) in emitLeadingFence()
2359 return Builder.CreateFence(Ord); in emitLeadingFence()
2366 AtomicOrdering Ord) const { in emitTrailingFence()
2367 if (isAcquireOrStronger(Ord)) in emitTrailingFence()
2368 return Builder.CreateFence(Ord); in emitTrailingFence()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h180 AtomicOrdering Ord) const override;
190 AtomicOrdering Ord) const override;
H A DLoongArchISelLowering.cpp4527 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
4548 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
4559 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
4562 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h206 AtomicOrdering Ord) const override;
208 AtomicOrdering Ord) const override;
H A DVEISelLowering.cpp1063 AtomicOrdering Ord) const { in emitLeadingFence()
1064 switch (Ord) { in emitLeadingFence()
1084 AtomicOrdering Ord) const { in emitTrailingFence()
1085 switch (Ord) { in emitTrailingFence()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h625 AtomicOrdering Ord) const override;
627 AtomicOrdering Ord) const override;
707 AtomicOrdering Ord) const override;
714 AtomicOrdering Ord) const override;
H A DRISCVISelLowering.cpp19320 return Builder.CreateFence(Ord); in emitLeadingFence()
19325 return Builder.CreateFence(Ord); in emitLeadingFence()
19326 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord)) in emitLeadingFence()
19336 return Builder.CreateFence(Ord); in emitTrailingFence()
19340 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord)) in emitTrailingFence()
19343 Ord == AtomicOrdering::SequentiallyConsistent) in emitTrailingFence()
19421 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
19432 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
19435 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
19493 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h650 AtomicOrdering Ord) const override;
652 AtomicOrdering Ord) const override;
658 AtomicOrdering Ord) const override;
660 AtomicOrdering Ord) const override;
H A DARMISelLowering.cpp4263 AtomicOrdering Ord = in LowerATOMIC_FENCE() local
4270 Ord == AtomicOrdering::Release) { in LowerATOMIC_FENCE()
21272 AtomicOrdering Ord) const { in emitLeadingFence()
21273 switch (Ord) { in emitLeadingFence()
21297 AtomicOrdering Ord) const { in emitTrailingFence()
21298 switch (Ord) { in emitTrailingFence()
21508 AtomicOrdering Ord) const { in emitLoadLinked()
21510 bool IsAcquire = isAcquireOrStronger(Ord); in emitLoadLinked()
21552 AtomicOrdering Ord) const { in emitStoreConditional()
21554 bool IsRelease = isReleaseOrStronger(Ord); in emitStoreConditional()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp113 Coloring(ArrayRef<Node> Ord) : Order(Ord) { in Coloring()
337 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) { in PermNetwork()
338 Order.assign(Ord.data(), Ord.data()+Ord.size()); in PermNetwork()
385 ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ForwardDeltaNetwork()
399 ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ReverseDeltaNetwork()
413 BenesNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord, 2) {} in BenesNetwork()
H A DHexagonGenInsert.cpp387 : MaxSize(MaxORLSize), Ord(RO) {} in OrderedRegisterList()
414 const RegisterOrdering &Ord; member in __anon9aeb66ce0311::OrderedRegisterList
443 iterator L = llvm::lower_bound(Seq, VR, Ord); in insert()
456 iterator L = llvm::lower_bound(Seq, VR, Ord); in remove()
H A DHexagonISelLowering.h350 AtomicOrdering Ord) const override;
352 AtomicOrdering Ord) const override;
H A DHexagonISelLowering.cpp3840 AtomicOrdering Ord) const { in emitLoadLinked()
3858 AtomicOrdering Ord) const { in emitStoreConditional()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h907 AtomicOrdering Ord) const override;
909 AtomicOrdering Ord) const override;
923 AtomicOrdering Ord) const override;
928 AtomicOrdering Ord) const override;
H A DPPCISelLowering.cpp11812 AtomicOrdering Ord) const { in emitLeadingFence()
11813 if (Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
11815 if (isReleaseOrStronger(Ord)) in emitLeadingFence()
11822 AtomicOrdering Ord) const { in emitTrailingFence()
11823 if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) { in emitTrailingFence()
18601 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
18623 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
18637 emitLeadingFence(Builder, CI, Ord); in emitMaskedAtomicCmpXchgIntrinsic()
18640 emitTrailingFence(Builder, CI, Ord); in emitMaskedAtomicCmpXchgIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
519 for (auto Reg : Ord) { in scavengeRegister()
H A DAArch64ISelLowering.h762 AtomicOrdering Ord) const override;
764 AtomicOrdering Ord) const override;
H A DAArch64FastISel.cpp2191 AtomicOrdering Ord = SI->getOrdering(); in selectStore() local
2193 if (isReleaseOrStronger(Ord)) { in selectStore()
/freebsd-14.2/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DCodeViewYAMLSymbols.cpp195 ThunkOrdinal &Ord) { in enumeration() argument
198 io.enumCase(Ord, E.Name.str().c_str(), static_cast<ThunkOrdinal>(E.Value)); in enumeration()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2089 Value *Addr, AtomicOrdering Ord) const { in emitLoadLinked() argument
2096 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional() argument
2108 AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic() argument
2142 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic() argument
2179 AtomicOrdering Ord) const;
2183 AtomicOrdering Ord) const;
/freebsd-14.2/contrib/llvm-project/clang/lib/Sema/
H A DSemaOverload.cpp12126 if (int Ord = CompareConversions(*L, *R)) in operator ()() local
12127 return Ord < 0; in operator ()()
12180 if (int Ord = CompareConversions(*L, *R)) in operator ()() local
12181 return Ord < 0; in operator ()()

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