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Searched refs:OpcodeMask (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch32.h211 static constexpr uint32_t OpcodeMask = 0x0f000000;
215 static constexpr uint32_t OpcodeMask = 0x0e000000;
223 static constexpr uint32_t OpcodeMask = 0x0ff00000;
238 static constexpr HalfWords OpcodeMask{0xf800, 0x9000};
244 static constexpr HalfWords OpcodeMask{0xf800, 0xc000};
251 static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.h145 const SmallBitVector &OpcodeMask,
275 const SmallBitVector &OpcodeMask) const;
H A DX86TargetTransformInfo.cpp1464 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
1466 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6004 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr()
6013 assert(OpcodeMask.size() == NumElements && "Mask and VecTy are incompatible"); in isLegalAltInstr()
6019 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h792 const SmallBitVector &OpcodeMask) const;
1264 const SmallBitVector &OpcodeMask,
1853 const SmallBitVector &OpcodeMask) const = 0;
1972 const SmallBitVector &OpcodeMask,
2345 const SmallBitVector &OpcodeMask) const override { in isLegalAltInstr() argument
2346 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
2594 const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
2596 return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
H A DTargetTransformInfoImpl.h301 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr() argument
570 const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp476 const SmallBitVector &OpcodeMask) const { in isLegalAltInstr()
477 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
881 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const { in getAltInstrCost() argument
883 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Daarch32.cpp262 return (Wd & FixupInfo<K>::OpcodeMask) == FixupInfo<K>::Opcode; in checkOpcodeArm()
267 return (Hi & FixupInfo<K>::OpcodeMask.Hi) == FixupInfo<K>::Opcode.Hi && in checkOpcodeThumb()
268 (Lo & FixupInfo<K>::OpcodeMask.Lo) == FixupInfo<K>::Opcode.Lo; in checkOpcodeThumb()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp4350 SmallBitVector OpcodeMask(TE->Scalars.size(), false); in reorderTopToBottom() local
4353 OpcodeMask.set(Lane); in reorderTopToBottom()
4355 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
8468 SmallBitVector OpcodeMask(E->Scalars.size(), false); in getEntryCost() local
8471 OpcodeMask.set(Lane); in getEntryCost()
8474 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in getEntryCost()
8476 VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getEntryCost()