| /freebsd-14.2/contrib/llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
163 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
164 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
187 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
210 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11000110_sssscccc() local
220 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11000111_0000iiii() local
223 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop "); in Decode_11000111_0000iiii()
224 if ((Opcode1 & 0xf0) == 0x00 && Opcode1) in Decode_11000111_0000iiii()
231 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11001000_sssscccc() local
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 144 unsigned Opcode1,
274 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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| H A D | X86TargetTransformInfo.cpp | 1464 unsigned Opcode1, const SmallBitVector &OpcodeMask, in getAltInstrCost() argument
1466 if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) in getAltInstrCost()
6003 unsigned Opcode1, in isLegalAltInstr() argument
6019 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
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| H A D | X86ISelLowering.cpp | 40376 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
40377 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
40378 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
40382 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
40389 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 791 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1263 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1852 unsigned Opcode1,
1971 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2344 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
2346 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
2593 unsigned Opcode1, in getAltInstrCost() argument
2596 return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
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| H A D | TargetTransformInfoImpl.h | 300 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
569 unsigned Opcode1, in getAltInstrCost() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 475 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
477 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
880 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in getAltInstrCost() argument
883 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getAltInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 852 bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1, in areOpcodesEqualOrInverse() argument
854 return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2; in areOpcodesEqualOrInverse()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 171 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
175 (BO->getOpcode() == Opcode1 || BO->getOpcode() == Opcode2)) in isReassociableOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1237 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 4348 unsigned Opcode1 = TE->getAltOpcode(); in reorderTopToBottom() local
4352 if (cast<Instruction>(TE->Scalars[Lane])->getOpcode() == Opcode1) in reorderTopToBottom()
4355 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
8466 unsigned Opcode1 = E->getAltOpcode(); in getEntryCost() local
8470 if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1) in getEntryCost()
8474 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in getEntryCost()
8476 VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); in getEntryCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4224 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
4233 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
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| H A D | AArch64ISelLowering.cpp | 16535 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
16543 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
16545 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5593 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax() local
5594 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
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