| H A D | AMDGPUDisassembler.cpp | 137 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ argument 144 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ argument 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 157 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ argument 158 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 163 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 169 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 174 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 186 DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth) [all …]
|