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Searched refs:OpRC (Results 1 – 9 of 9) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp137 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
139 assert(OpRC && "Not a valid register class"); in pickBestRegisterForUndef()
144 if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
H A DMachineInstr.cpp973 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
979 if (OpRC) in getRegClassConstraintEffect()
980 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
983 } else if (OpRC) in getRegClassConstraintEffect()
984 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
H A DRegAllocFast.cpp1245 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1250 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1650 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1651 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1658 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1672 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1692 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1693 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1694 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1696 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
1697 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
1702 Register VStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp314 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
316 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
318 if (OpRC) { in AddRegisterOperand()
327 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
329 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
330 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
331 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
390 const TargetRegisterClass *OpRC = in AddOperand() local
397 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp115 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
121 if (OpRC) { in constrainOperandRegClass()
127 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI))) in constrainOperandRegClass()
128 OpRC = SubRC; in constrainOperandRegClass()
130 OpRC = TRI.getAllocatableClass(OpRC); in constrainOperandRegClass()
133 if (!OpRC) { in constrainOperandRegClass()
149 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1773 const TargetRegisterClass *OpRC = in tryFoldRegSequence() local
1775 if (!OpRC || !TRI->isVectorSuperClass(OpRC)) in tryFoldRegSequence()
H A DSIInstrInfo.cpp6110 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
6114 if (DstRC == OpRC) in legalizeGenericOperand()
6471 const TargetRegisterClass *OpRC = in legalizeOperands() local
6473 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
6474 VRC = OpRC; in legalizeOperands()
6476 SRC = OpRC; in legalizeOperands()
6533 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
6534 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
6535 if (VRC == OpRC) in legalizeOperands()
8400 const TargetRegisterClass *OpRC = in findUsedSGPR() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1911 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1913 return OpRC->hasSubClassEq(RRC); in validateReg()