Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance
1708 const MulDivRemEntry::MulDivRemResult &OpEntry = in selectMulDivRem() local1721 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectMulDivRem()1726 if (OpEntry.OpSignExtend) { in selectMulDivRem()1727 if (OpEntry.IsOpSigned) in selectMulDivRem()1729 TII.get(OpEntry.OpSignExtend)); in selectMulDivRem()1757 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpMulDivRem)) in selectMulDivRem()1768 if (OpEntry.ResultReg == X86::AH && STI.is64Bit()) { in selectMulDivRem()1790 .addReg(OpEntry.ResultReg); in selectMulDivRem()
1943 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1953 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1955 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1956 if (OpEntry.IsOpSigned) in X86SelectDivRem()1958 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1984 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()1996 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2014 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()