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Searched refs:Op3 (Results 1 – 25 of 35) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
527 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
540 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
553 unsigned Op1, Op2, Op3; in Decode2RUSBitpInstruction() local
566 unsigned Op1, Op2, Op3; in DecodeL3RInstruction() local
580 unsigned Op1, Op2, Op3; in DecodeL3RSrcDstInstruction() local
595 unsigned Op1, Op2, Op3; in DecodeL2RUSInstruction() local
609 unsigned Op1, Op2, Op3; in DecodeL2RUSBitpInstruction() local
657 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
677 unsigned Op1, Op2, Op3; in DecodeL4RSrcDstInstruction() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h27 SDValue Op3, Align Alignment, bool isVolatile,
33 SDValue Op1, SDValue Op2, SDValue Op3,
39 SDValue Op3, Align Alignment, bool IsVolatile,
H A DWebAssemblySelectionDAGInfo.cpp38 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
H A DSelectionDAG.h1632 SDValue Op3);
1634 SDValue Op3, SDValue Op4);
1636 SDValue Op3, SDValue Op4, SDValue Op5);
1664 SDValue Op1, SDValue Op2, SDValue Op3);
1699 SDValue Op1, SDValue Op2, SDValue Op3);
1705 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1712 SDValue Op3);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
111 if (Op3.isGlobal()) in getAddressFromInstr()
112 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
H A DX86FastISel.cpp169 unsigned Op1, unsigned Op2, unsigned Op3);
4038 unsigned Op2, unsigned Op3) { in fastEmitInst_rrrr() argument
4045 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
4052 .addReg(Op3); in fastEmitInst_rrrr()
4058 .addReg(Op3); in fastEmitInst_rrrr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h24 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h57 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp332 MachineInstr *Op3 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); in matchFPMed3ToClamp() local
333 if (Op3->getOpcode() == TargetOpcode::G_FCONSTANT) in matchFPMed3ToClamp()
334 return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0); in matchFPMed3ToClamp()
H A DR600InstrFormats.td28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp290 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
291 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
297 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1483 T2 Op3; member
1485 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1486 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1492 Op3.match(I->getOperand(2)); in match()
2245 const Opnd3 &Op3) {
2246 return m_Intrinsic<Intrinsic::masked_load>(Op0, Op1, Op2, Op3);
2253 const Opnd3 &Op3) {
2254 return m_Intrinsic<Intrinsic::masked_gather>(Op0, Op1, Op2, Op3);
2284 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
2286 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td411 (inst $Op3, $Op1, $Op2)>;
419 (inst $Op3, $Op1, $Op2)>;
427 (inst $Op3, $Op1, $Op2)>;
434 (inst $Op3, $Op1, $Op2)>;
477 (inst $Op1, $Op2, $Op3)>;
488 (inst $Op1, $Op2, $Op3)>;
495 (inst $Op1, $Op2, $Op3)>;
539 (inst $Op1, $Op2, $Op3)>;
545 (inst $Op1, $Op2, vt3:$Op3)>;
613 (inst $Op2, $Op3, $Op1)>;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp106 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
113 switch (Op3.getImm()) { in printInst()
148 if (Op2.isImm() && Op3.isImm()) { in printInst()
152 int64_t imms = Op3.getImm(); in printInst()
186 if (Op2.getImm() > Op3.getImm()) { in printInst()
194 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; in printInst()
207 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1; in printInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp6137 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
6138 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
6159 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
6226 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
6242 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
6265 NewOp3, Op3.getStartLoc(), Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
6290 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
6306 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
6347 if ((Op1.isToken() && Op2.isNeonVectorReg() && Op3.isImm()) || in MatchAndEmitInstruction()
6348 (Op1.isNeonVectorReg() && Op2.isToken() && Op3.isImm())) { in MatchAndEmitInstruction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1343 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1347 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1351 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1367 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1375 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1385 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1389 .add(Op3); in expandPostRAPseudo()
1400 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1421 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1422 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
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H A DHexagonSplitDouble.cpp903 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
904 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
905 int64_t Sh64 = Op3.getImm(); in splitAslOr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h136 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
240 TmpInst.addOperand(Op3); in emitRRRX()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp10199 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
10205 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
10206 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
10212 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
10213 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
10308 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
10513 SDValue Op3) { in getMachineNode() argument
10515 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
10537 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
10559 SDValue Op3) { in getMachineNode() argument
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H A DSelectionDAGBuilder.cpp6139 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6150 Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
6181 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6188 Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, in visitIntrinsicCall()
6215 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6225 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
6875 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6877 Op1.getValueType(), Op1, Op2, Op3)); in visitIntrinsicCall()
6886 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6888 Op1, Op2, Op3, DAG, TLI)); in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DVerifier.cpp5720 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
5721 Check(Op3->getType()->isIntegerTy(), in visitIntrinsicCall()
5723 Check(Op3->getBitWidth() <= 32, in visitIntrinsicCall()
5728 Check(Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
5732 Check(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6497 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm() local
6499 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6502 auto Op3Reg = Op3.getReg(); in tryConvertingToTwoOperandForm()
6845 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias() local
6849 if (!Op3.isGPRMem()) in fixupGNULDRDAlias()
6927 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand() local
6928 if (!Op3.isReg() || Op3.getReg() != RNext) in CDEConvertDualRegOperand()
6929 return Error(Op3.getStartLoc(), "operand must be a consecutive register"); in CDEConvertDualRegOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp3030 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall3() local
3033 const APFloat &C3 = Op3->getValueAPF(); in ConstantFoldScalarCall3()

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