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Searched refs:Op2 (Results 1 – 25 of 129) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
155 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
271 if (Op2.isImm()) { in getSplsOpValue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp322 unsigned Op1, Op2; in Decode2RInstruction() local
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
348 unsigned Op1, Op2; in DecodeR2RInstruction() local
361 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
375 unsigned Op1, Op2; in DecodeRUSInstruction() local
388 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
401 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
486 unsigned Op1, Op2; in DecodeL2RInstruction() local
500 unsigned Op1, Op2; in DecodeLR2RInstruction() local
514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
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/freebsd-14.2/sys/contrib/dev/acpica/compiler/
H A Dasltree.c650 ACPI_PARSE_OBJECT *Op2) in TrLinkPeerOp() argument
658 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); in TrLinkPeerOp()
661 if ((!Op1) && (!Op2)) in TrLinkPeerOp()
669 if (!Op2) in TrLinkPeerOp()
676 return (Op2); in TrLinkPeerOp()
679 if (Op1 == Op2) in TrLinkPeerOp()
702 Next->Asl.Next = Op2; in TrLinkPeerOp()
795 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode): NULL); in TrLinkChildOp()
811 if (!Op1 || !Op2) in TrLinkChildOp()
816 Op1->Asl.Child = Op2; in TrLinkChildOp()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp253 const MachineMemOperand &Op2, in alias() argument
255 if (!Op1.getValue() || !Op2.getValue()) in alias()
258 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
260 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
265 MemoryLocation(Op2.getValue(), Overlapb, in alias()
266 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
278 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
279 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp169 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
170 if (Op1.getType() != Op2.getType()) in isSameOperand()
175 return Op1.getReg() == Op2.getReg(); in isSameOperand()
177 return Op1.getImm() == Op2.getImm(); in isSameOperand()
293 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
300 if (Op2.isImm()) { in isSuitableAluInstr()
313 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
314 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
315 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
317 } else if (Op2.isReg()) { in isSuitableAluInstr()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
164 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
165 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
176 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
179 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp117 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
118 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
124 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0)) in optimizeVccBranch()
129 if (Op2.isReg()) { in optimizeVccBranch()
130 SReg = Op2.getReg(); in optimizeVccBranch()
159 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
163 } else if (Op2.isImm()) { in optimizeVccBranch()
164 MaskValue = Op2.getImm(); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp155 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair() local
156 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
157 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
158 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
174 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
176 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
177 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
H A DWebAssemblyPeephole.cpp141 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
142 if (!Op2.isReg()) in runOnMachineFunction()
147 Register NewReg = Op2.getReg(); in runOnMachineFunction()
H A DWebAssemblySelectionDAGInfo.cpp37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp289 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
291 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
293 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
294 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
295 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
296 || Op2.getToken() == "le64") in PreMatchCheck()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td428 // Name, Op1, Op2
452 // Name, Op1, Op2, Crm_high
830 // Op0 Op1 CRn CRm Op2
835 // Op0 Op1 CRn CRm Op2
842 // Op0 Op1 CRn CRm Op2
1401 // Op0 Op1 CRn CRm Op2
1443 // Op0 Op1 CRn CRm Op2
1466 // Op0 Op1 CRn CRm Op2
1497 // Op0 Op1 CRn CRm Op2
1513 // Op0 Op1 CRn CRm Op2
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp346 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
726 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
743 if (!Op2.isReg()) { in splitCombine()
745 .add(Op2); in splitCombine()
748 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
780 int64_t Sh64 = Op2.getImm(); in splitShift()
918 unsigned RS2 = getRegState(Op2); in splitAslOr()
945 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
962 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
973 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp153 const MCOperand &Op2 = MI->getOperand(opNum + 1); in printMemOperand() local
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
165 (Op2.isImm() && Op2.getImm() == 0)); in printMemOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp302 auto Op2 = N->getOperand(2); in selectAddCarry() local
306 if (isNullConstant(Op2)) { in selectAddCarry()
312 } else if (isOneConstant(Op2)) { in selectAddCarry()
321 Dl, {Type0, Type1}, {Op0, Op1, Op2}); in selectAddCarry()
345 auto Op2 = N->getOperand(2); in selectSubCarry() local
349 if (isNullConstant(Op2)) { in selectSubCarry()
355 } else if (isOneConstant(Op2)) { in selectSubCarry()
362 auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2); in selectSubCarry()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp341 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
344 << "Op2: " << Op2 << "\n"); in identicalOperands()
346 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
362 if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() && in identicalOperands()
363 Op2.getReg().isVirtual()) { in identicalOperands()
365 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands()
H A DPPCMacroFusion.cpp73 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps() local
74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp87 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
329 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
334 if (Op1 && Op2) in insertOperandRuntimeCheck()
335 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
337 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp166 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); in getMemoryOpValue() local
167 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
168 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1465 T1 Op2; member
1467 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1482 T1 Op2; member
1485 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1486 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1568 T1 Op2; member
1571 Shuffle_match(const T0 &Op1, const T1 &Op2, const T2 &Mask) in Shuffle_match()
1572 : Op1(Op1), Op2(Op2), Mask(Mask) {} in Shuffle_match()
2270 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
2335 return m_Intrinsic<Intrinsic::fshl>(Op0, Op1, Op2);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp114 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
519 const MachineMemOperand &Op2) const { in alias()
520 if (!Op1.getValue() || !Op2.getValue()) in alias()
523 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
525 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
529 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); in alias()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp297 Val = Op1.second + Op2.second; in execute()
301 Val = Op1.second - Op2.second; in execute()
307 Val = Op1.second * Op2.second; in execute()
314 Val = Op1.second / Op2.second; in execute()
320 Val = Op1.second % Op2.second; in execute()
326 Val = Op1.second | Op2.second; in execute()
332 Val = Op1.second ^ Op2.second; in execute()
338 Val = Op1.second & Op2.second; in execute()
344 Val = Op1.second << Op2.second; in execute()
3533 if (Op1.isReg() && Op2.isReg() && in ParseInstruction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp105 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
148 if (Op2.isImm() && Op3.isImm()) { in printInst()
151 int64_t immr = Op2.getImm(); in printInst()
186 if (Op2.getImm() > Op3.getImm()) { in printInst()
214 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
218 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && in printInst()
242 printRegName(O, Op2.getReg()); in printInst()
257 printRegName(O, Op2.getReg()); in printInst()
913 unsigned Op2Val = Op2.getImm(); in printSysAlias()
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