Searched refs:OneRegVT (Results 1 – 1 of 1) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3816 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerBUILD_VECTOR() local
3817 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerBUILD_VECTOR()
3830 DAG.getNode(ISD::BUILD_VECTOR, DL, OneRegVT, OneVRegOfOps); in lowerBUILD_VECTOR()
4708 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerShuffleViaVRegSplitting() local
4709 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerShuffleViaVRegSplitting()
4726 SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget); in lowerShuffleViaVRegSplitting()
4727 SubVec = DAG.getVectorShuffle(OneRegVT, DL, SubVec, SubVec, SrcSubMask); in lowerShuffleViaVRegSplitting()
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