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Searched refs:ORI (Results 1 – 25 of 30) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMatInt.cpp35 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
41 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def116 FUSION_FEATURE(OriOris, hasWideImmFusion, 1, FUSION_OP_SET(ORI, ORI8),
121 FUSION_OP_SET(ORI, ORI8))
125 FUSION_OP_SET(ORI, ORI8))
H A DPPCBack2BackFusion.def155 ORI,
693 ORI,
H A DPPCExpandISEL.cpp455 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI)) in populateBlocks()
H A DPPCPreEmitPeephole.cpp438 BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR) in runOnMachineFunction()
H A DPPCInstrInfo.cpp3313 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3383 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
3958 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
4657 case PPC::ORI: in simplifyToLI()
4663 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
5273 case PPC::ORI: in isSignOrZeroExtended()
H A DPPCAsmPrinter.cpp1519 MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0)); in emitInstruction()
1522 MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0)); in emitInstruction()
2883 MCInstBuilder(PPC::ORI).addReg(PPC::R0).addReg(PPC::R0).addImm(0)); in emitInstruction()
H A DPPCFrameLowering.cpp1298 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::ORI8 : PPC::ORI), TempReg) in inlineStackProbe()
1590 : PPC::ORI ); in emitEpilogue()
2568 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()
H A DPPCScheduleP7.td185 (instregex "^(X)?ORI(S)?(8)?$"),
H A DPPCInstrInfo.td2335 def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
2418 def : InstAlias<"nop", (ORI R0, R0, 0)>;
3113 // Arbitrary immediate support. Implement in terms of LIS/ORI.
3115 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
3128 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
5110 dag Lo1 = (ORI (LIS 0x5555), 0x5555);
5111 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
5112 dag Lo2 = (ORI (LIS 0x3333), 0x3333);
5113 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
5114 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
[all …]
H A DPPCFastISel.cpp1321 Opc = PPC::ORI; in SelectBinaryIntOp()
2137 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg) in PPCMaterialize32BitInt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DPartialInlining.cpp184 SmallVector<OutlineRegionInfo, 4> ORI; member
502 OutliningInfo->ORI.push_back(RegInfo); in computeOutliningColdRegionsInfo()
984 OI->ORI) { in FunctionCloner()
996 ClonedOMRI->ORI.push_back(MappedRegionInfo); in FunctionCloner()
1093 if (ClonedOMRI->ORI.empty()) in doMultiRegionFunctionOutlining()
1110 ClonedOMRI->ORI) { in doMultiRegionFunctionOutlining()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp219 case RISCV::ORI: { in hasAllNBitUsers()
362 case RISCV::ORI: in isSignExtendingOpW()
490 case RISCV::ORI: in isSignExtendedW()
H A DRISCVInstrInfoZb.td85 // Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
110 // Check if (or r, imm) can be optimized to (BSETI (ORI r, i0), i1),
580 (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
H A DRISCVExpandPseudoInsts.cpp222 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break; in expandCCOp()
H A DRISCVInstrInfo.td653 def ORI : ALU_ri<0b110, "ori">;
1019 (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1239 def : PatGprSimm12<or, ORI>;
1993 (ORI GPR:$rs1, u32simm12:$imm)>;
2112 (ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
H A DRISCVAsmPrinter.cpp667 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
H A DRISCVInstrInfo.cpp1338 case RISCV::ORI: return RISCV::PseudoCCORI; break; in getPredicatedOpcode()
1568 case RISCV::ORI: in isAsCheapAsAMove()
H A DRISCVISelDAGToDAG.cpp668 case ISD::OR: BinOpc = RISCV::ORI; break; in tryShrinkShlLogicImm()
2983 case RISCV::ORI: { in hasAllNBitUsers()
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h125 I_TYPE_INST(ORI);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
H A DEmulateInstructionRISCV.cpp441 {"ORI", 0x707F, 0x6013, DecodeIType<ORI>},
755 bool operator()(ORI inst) { in operator ()()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp787 case LoongArch::ORI: in emitLAInstSeq()
851 LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_ABS_LO12)); in emitLoadAddressAbs()
968 LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12)); in emitLoadAddressTLSLE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp203 case LoongArch::ORI: in movImm()
H A DLoongArchExpandPseudoInsts.cpp210 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01) in expandLoadAddressTLSLE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td943 // Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
949 /* Disable display, so we don't override ORI */ 0>;

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