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Searched refs:NumSubRegs (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp83 unsigned NumSubRegs; member
1510 if (i == NumSubRegs) { in buildSpillLoadStore()
1775 SB.NumSubRegs == 1 in spillSGPR()
1829 SB.NumSubRegs == 1 in spillSGPR()
1850 if (SB.NumSubRegs > 1) { in spillSGPR()
1891 SB.NumSubRegs == 1 in restoreSGPR()
1924 SB.NumSubRegs == 1 in restoreSGPR()
1971 SB.NumSubRegs == 1 in spillEmergencySGPR()
1984 if (SB.NumSubRegs > 1) { in spillEmergencySGPR()
1987 if (i + 1 == SB.NumSubRegs) in spillEmergencySGPR()
[all …]
H A DSIFrameLowering.cpp239 unsigned NumSubRegs; member in llvm::PrologEpilogSGPRSpillBuilder
253 for (unsigned I = 0, DwordOff = 0; I < NumSubRegs; ++I) { in saveToMemory()
254 Register SubReg = NumSubRegs == 1 in saveToMemory()
272 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
274 for (unsigned I = 0; I < NumSubRegs; ++I) { in saveToVGPRLane()
275 Register SubReg = NumSubRegs == 1 in saveToVGPRLane()
302 Register SubReg = NumSubRegs == 1 in restoreFromMemory()
318 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
320 for (unsigned I = 0; I < NumSubRegs; ++I) { in restoreFromVGPRLane()
321 Register SubReg = NumSubRegs == 1 in restoreFromVGPRLane()
[all …]
H A DSIInstrInfo.cpp6169 unsigned NumSubRegs = RegSize / 32; in emitLoadScalarOpsFromVGPRLoop() local
6172 if (NumSubRegs == 1) { in emitLoadScalarOpsFromVGPRLoop()
6200 assert(NumSubRegs % 2 == 0 && NumSubRegs <= 32 && in emitLoadScalarOpsFromVGPRLoop()
6203 for (unsigned Idx = 0; Idx < NumSubRegs; Idx += 2) { in emitLoadScalarOpsFromVGPRLoop()
6231 if (NumSubRegs <= 2) in emitLoadScalarOpsFromVGPRLoop()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp329 const MCInstrDesc &MCID, unsigned int NumSubRegs, in copyPhysSubRegs() argument
334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { in copyPhysSubRegs()
394 unsigned int NumSubRegs = 2; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
400 unsigned int NumSubRegs = 2; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp27107 unsigned NumSubRegs = RegisterVT.getFixedSizeInBits() / 128; in getVectorTypeBreakdownForCallingConv() local
27108 NumIntermediates *= NumSubRegs; in getVectorTypeBreakdownForCallingConv()
27109 NumRegs *= NumSubRegs; in getVectorTypeBreakdownForCallingConv()