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Searched refs:NumSubElts (Results 1 – 16 of 16) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h133 int NumSubElts = SubVTy->getNumElements(); in getExtractSubvectorOverhead() local
135 (Index + NumSubElts) <= in getExtractSubvectorOverhead()
143 for (int i = 0; i != NumSubElts; ++i) { in getExtractSubvectorOverhead()
161 int NumSubElts = SubVTy->getNumElements(); in getInsertSubvectorOverhead() local
163 (Index + NumSubElts) <= in getInsertSubvectorOverhead()
171 for (int i = 0; i != NumSubElts; ++i) { in getInsertSubvectorOverhead()
982 int NumSubElts; in improveShuffleKindFromMask() local
985 if (Index + NumSubElts > NumSrcElts) in improveShuffleKindFromMask()
1392 unsigned NumSubElts = NumElts / Factor; variable
1454 for (unsigned Elm = 0; Elm < NumSubElts; Elm++)
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h1315 int NumSubElts, SubIndex; in getInstructionCost() local
1327 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1331 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), in getInstructionCost()
1378 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) in getInstructionCost()
1381 SubIndex, FixedVectorType::get(VecTy->getScalarType(), NumSubElts), in getInstructionCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DInstructions.cpp2393 NumSubElts = NumSub1Elts; in isInsertSubvectorMask()
2405 NumSubElts = NumSub0Elts; in isInsertSubvectorMask()
2682 static int matchShuffleAsBitRotate(ArrayRef<int> Mask, int NumSubElts) { in matchShuffleAsBitRotate() argument
2684 assert((NumElts % NumSubElts) == 0 && "Illegal shuffle mask"); in matchShuffleAsBitRotate()
2687 for (int i = 0; i != NumElts; i += NumSubElts) { in matchShuffleAsBitRotate()
2688 for (int j = 0; j != NumSubElts; ++j) { in matchShuffleAsBitRotate()
2692 if (M < i || M >= i + NumSubElts) in matchShuffleAsBitRotate()
2694 int Offset = (NumSubElts - (M - (i + j))) % NumSubElts; in matchShuffleAsBitRotate()
2705 unsigned MaxSubElts, unsigned &NumSubElts, unsigned &RotateAmt) { in isBitRotateMask() argument
2706 for (NumSubElts = MinSubElts; NumSubElts <= MaxSubElts; NumSubElts *= 2) { in isBitRotateMask()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1311 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedBits() local
1314 DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedBits()
1407 unsigned NumSubElts = in SimplifyDemandedBits() local
3223 unsigned NumSubElts = SubVT.getVectorNumElements(); in SimplifyDemandedVectorElts() local
3226 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedVectorElts()
3231 KnownUndef.insertBits(SubUndef, i * NumSubElts); in SimplifyDemandedVectorElts()
3232 KnownZero.insertBits(SubZero, i * NumSubElts); in SimplifyDemandedVectorElts()
3241 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts); in SimplifyDemandedVectorElts()
9786 unsigned NumSubElts = SubEC.getKnownMinValue(); in clampDynamicVectorIndex() local
9803 if (isPowerOf2_32(NElts) && NumSubElts == 1) { in clampDynamicVectorIndex()
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H A DSelectionDAG.cpp3204 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in computeKnownBits() local
3205 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in computeKnownBits()
3207 DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); in computeKnownBits()
4755 unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); in ComputeNumSignBits() local
4756 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); in ComputeNumSignBits()
4758 DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); in ComputeNumSignBits()
11966 auto PartialReduction = [&](SDValue Op, unsigned NumSubElts) { in matchBinOpReduction() argument
11971 EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts); in matchBinOpReduction()
H A DDAGCombiner.cpp25585 int NumSubElts = SubVT.getVectorNumElements(); in visitVECTOR_SHUFFLE() local
25586 assert((NumElts % NumSubElts) == 0 && "Subvector mismatch"); in visitVECTOR_SHUFFLE()
25598 for (int SubIdx = 0; SubIdx != (int)NumElts; SubIdx += NumSubElts) { in visitVECTOR_SHUFFLE()
25604 InsertionMask.begin() + SubIdx + NumSubElts, in visitVECTOR_SHUFFLE()
25605 NumElts + (SubVec * NumSubElts)); in visitVECTOR_SHUFFLE()
26557 int NumSubElts = NumElts * Split; in XformToShuffleWithZero() local
26561 for (int i = 0; i != NumSubElts; ++i) { in XformToShuffleWithZero()
26568 Indices.push_back(i + NumSubElts); in XformToShuffleWithZero()
26589 Indices.push_back(i + NumSubElts); in XformToShuffleWithZero()
26596 EVT ClearVT = EVT::getVectorVT(*DAG.getContext(), ClearSVT, NumSubElts); in XformToShuffleWithZero()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstructions.h2322 int &NumSubElts, int &Index);
2324 int &NumSubElts, int &Index) {
2332 return isInsertSubvectorMask(MaskAsInts, NumSrcElts, NumSubElts, Index);
2336 bool isInsertSubvectorMask(int &NumSubElts, int &Index) const {
2344 return isInsertSubvectorMask(ShuffleMask, NumSrcElts, NumSubElts, Index);
2440 unsigned &NumSubElts, unsigned &RotateAmt);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1505 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1506 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
1515 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && in getShuffleCost()
1516 (NumSubElts % OrigSubElts) == 0 && in getShuffleCost()
1521 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && in getShuffleCost()
1527 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); in getShuffleCost()
1552 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
1553 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
H A DX86InstCombineIntrinsic.cpp265 for (unsigned i = 0, NumSubElts = 64 / BitWidth; i != NumSubElts; ++i) { in simplifyX86immShift() local
266 unsigned SubEltIdx = (NumSubElts - 1) - i; in simplifyX86immShift()
H A DX86ISelLowering.cpp4800 APInt UndefSubElts(NumSubElts, 0); in getTargetConstantBitsFromNode()
4870 if ((BaseIdx + NumSubElts) != NumSrcElts) in getTargetConstantBitsFromNode()
5587 if (M < Idx || (Idx + NumSubElts) <= M) in getTargetShuffleAndZeroables()
5794 NumSubElts *= (MaxElts / NumElts); in getFauxShuffleMask()
5825 if (SubMask.size() != NumSubElts) { in getFauxShuffleMask()
5828 if ((NumSubElts % SubMask.size()) == 0) { in getFauxShuffleMask()
5835 NumSubElts = SubMask.size(); in getFauxShuffleMask()
5850 int InputIdx = M / NumSubElts; in getFauxShuffleMask()
6309 uint64_t SubIdx = Index / NumSubElts; in getShuffleScalarElt()
6310 uint64_t SubElt = Index % NumSubElts; in getShuffleScalarElt()
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H A DX86ISelDAGToDAG.cpp1071 unsigned NumSubElts = VT.getSizeInBits() / MaxVT.getScalarSizeInBits(); in PreprocessISelDAG() local
1072 MVT SubVT = MVT::getVectorVT(MaxVT.getScalarType(), NumSubElts); in PreprocessISelDAG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18413 (IdxVal != 0 && IdxVal != NumSubElts)) in performInsertSubvectorCombine()
19330 int NumSubElts = NumElts / 4; in isLoadOrMultipleLoads() local
19331 for (int I = 0; I < NumSubElts; I++) { in isLoadOrMultipleLoads()
19334 SV1->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
19335 SV1->getMaskElt(I + NumSubElts * 2) != I + NumSubElts * 2 || in isLoadOrMultipleLoads()
19340 SV2->getMaskElt(I + NumSubElts) != I + NumSubElts || in isLoadOrMultipleLoads()
19491 int Hi = NumSubElts, Lo = 0; in performExtBinopLoadFold()
19494 LowMask[i * NumSubElts + j] = Lo++; in performExtBinopLoadFold()
19495 HighMask[i * NumSubElts + j] = Hi++; in performExtBinopLoadFold()
19497 Lo += NumSubElts; in performExtBinopLoadFold()
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H A DAArch64TargetTransformInfo.cpp3968 int NumSubElts = SubLT.second.getVectorNumElements(); in getShuffleCost() local
3969 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) in getShuffleCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4393 int NumSubElts, Index; in lowerVECTOR_SHUFFLEAsVSlideup() local
4394 if (!ShuffleVectorInst::isInsertSubvectorMask(Mask, NumElts, NumSubElts, in lowerVECTOR_SHUFFLEAsVSlideup()
4410 if (NumSubElts + Index >= (int)NumElts) in lowerVECTOR_SHUFFLEAsVSlideup()
4415 SDValue VL = DAG.getConstant(NumSubElts + Index, DL, XLenVT); in lowerVECTOR_SHUFFLEAsVSlideup()
4632 unsigned NumSubElts, RotateAmt; in lowerVECTOR_SHUFFLEAsRotate() local
4634 NumElts, NumSubElts, RotateAmt)) in lowerVECTOR_SHUFFLEAsRotate()
4636 MVT RotateVT = MVT::getVectorVT(MVT::getIntegerVT(EltSizeInBits * NumSubElts), in lowerVECTOR_SHUFFLEAsRotate()
4637 NumElts / NumSubElts); in lowerVECTOR_SHUFFLEAsRotate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp6909 int NumSubElts; in getShuffleCost() local
6911 Mask, NumSrcElts, NumSubElts, Index)) { in getShuffleCost()
6912 if (Index + NumSubElts > NumSrcElts && in getShuffleCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15655 unsigned NumSubElts = SubVT.getVectorNumElements(); in PerformInsertSubvectorCombine() local
15657 (IdxVal != 0 && IdxVal != NumSubElts)) in PerformInsertSubvectorCombine()
15668 DCI.DAG.getVectorIdxConstant(NumSubElts, DL)); in PerformInsertSubvectorCombine()