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Searched refs:NewVT (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1180 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local
1181 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1182 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1183 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1190 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1666 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local
1667 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1668 NewVT = EltTy; in getVectorTypeBreakdown()
1669 IntermediateVT = NewVT; in getVectorTypeBreakdown()
1671 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
231 EVT::getVectorVT(*DAG.getContext(), NewVT, OldEltCount * 2), OldVec); in ExpandRes_EXTRACT_VECTOR_ELT()
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
373 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
393 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp350 NewVT, Op); in ScalarizeVecRes_BITCAST()
2768 [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); }, in SplitVecRes_VECTOR_SHUFFLE()
6344 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST()
6363 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST()
7049 if (!NewVT) in GenWidenVectorLoads()
7053 MemVTs.push_back(*NewVT); in GenWidenVectorLoads()
7263 std::optional<EVT> NewVT = in GenWidenVectorStores() local
7265 if (!NewVT) in GenWidenVectorStores()
7267 MemVTs.push_back({*NewVT, 0}); in GenWidenVectorStores()
7277 EVT NewVT = Pair.first; in GenWidenVectorStores() local
[all …]
H A DDAGCombiner.cpp5133 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
5137 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
5204 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
5208 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
5388 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
5442 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
5631 NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, in PerformMinMaxFpToSatCombine()
5666 NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, in PerformUMinFpToSatCombine()
26220 EVT NewVT; in visitINSERT_SUBVECTOR() local
27586 if (NewVT == CurVT) in takeInexpensiveLog2()
[all …]
H A DTargetLowering.cpp236 EVT NewVT = VT; in findOptimalMemOpLowering() local
241 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering()
242 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
243 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering()
245 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering()
249 NewVT = MVT::f64; in findOptimalMemOpLowering()
256 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
257 if (NewVT == MVT::i8) in findOptimalMemOpLowering()
259 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering()
261 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering()
[all …]
H A DLegalizeDAG.cpp3425 EVT NewVT = in ExpandNode() local
3428 assert(NewVT.bitsEq(VT)); in ExpandNode()
3431 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3432 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3436 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3452 VT = NewVT; in ExpandNode()
H A DSelectionDAGBuilder.cpp7651 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltTy, in visitIntrinsicCall() local
7657 SDValue StepVec = DAG.getStepVector(DL, NewVT); in visitIntrinsicCall()
7658 SDValue SplatVL = DAG.getSplat(NewVT, DL, VL); in visitIntrinsicCall()
7659 SDValue StepVL = DAG.getNode(ISD::SUB, DL, NewVT, SplatVL, StepVec); in visitIntrinsicCall()
7660 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, Op); in visitIntrinsicCall()
7661 SDValue And = DAG.getNode(ISD::AND, DL, NewVT, StepVL, Ext); in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h132 EVT NewVT) const override { in shouldReduceLoadWidth() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp640 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local
649 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
680 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp396 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local
397 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn()
404 LLT NewLLT(NewVT); in lowerReturn()
406 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn()
409 if (NewVT.isVector()) { in lowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp772 EVT NewVT) const { in shouldReduceLoadWidth()
774 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
777 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
1488 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, in LowerCONCAT_VECTORS() local
1490 SDValue BV = DAG.getBuildVector(NewVT, SL, Args); in LowerCONCAT_VECTORS()
1516 EVT NewVT = NumElt == 2 in LowerEXTRACT_SUBVECTOR() local
1525 Tmp = DAG.getBuildVector(NewVT, SL, Args); in LowerEXTRACT_SUBVECTOR()
3786 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
3789 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3837 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
[all …]
H A DR600ISelLowering.cpp1696 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1699 NewVT = VT; in constBufferLoad()
1702 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp6006 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
6007 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
6008 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
6010 EVT SelectVT = NewVT; in ReplaceNodeResults()
6011 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
6020 if (NewVT != SelectVT) in ReplaceNodeResults()
6021 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
7715 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local
7719 ResultTypes[0] = NewVT; in lowerImage()
13160 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
[all …]
H A DAMDGPUISelDAGToDAG.cpp673 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
674 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h343 EVT NewVT) const override;
H A DHexagonISelLowering.cpp3815 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()
3817 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4030 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
4466 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
12110 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
12111 V1 = DAG.getBitcast(NewVT, V1); in tryWidenMaskForShuffle()
21286 MVT NewVT = in performLOADCombine() local
21319 SDValue UndefVector = DAG.getUNDEF(NewVT); in performLOADCombine()
26668 EVT NewVT = in LowerFixedLengthVECTOR_SHUFFLEToSVE() local
27095 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdownForCallingConv()
27096 NewVT = EltTy; in getVectorTypeBreakdownForCallingConv()
27098 IntermediateVT = NewVT; in getVectorTypeBreakdownForCallingConv()
[all …]
H A DAArch64ISelLowering.h654 EVT NewVT) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5636 EVT NewVT = MVT::v4i32; in PerformLOADCombine() local
5637 EVT EltVT = NewVT.getVectorElementType(); in PerformLOADCombine()
5638 unsigned NumElts = NewVT.getVectorNumElements(); in PerformLOADCombine()
5643 SDValue NewLoad = DAG.getMemIntrinsicNode(Opc, DL, RetVTList, Ops, NewVT, in PerformLOADCombine()
5652 {DCI.DAG.getBitcast(VT, DCI.DAG.getBuildVector(NewVT, DL, Elts)), in PerformLOADCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1418 EVT NewVT) const override;
H A DX86ISelLowering.cpp7742 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
7744 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
7745 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
12048 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
12049 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
17582 V1 = DAG.getBitcast(NewVT, V1); in lowerVECTOR_SHUFFLE()
17583 V2 = DAG.getBitcast(NewVT, V2); in lowerVECTOR_SHUFFLE()
27716 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) && in LowerVectorCTLZ_AVX512CDI()
30993 Op = DAG.getNode(ISD::CTPOP, DL, NewVT, Op); in LowerVectorCTPOP()
39917 MVT NewVT = in combineTargetShuffle() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2629 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
2632 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
2633 Value *V1 = Builder.CreateIntCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/freebsd-14.2/contrib/llvm-project/clang/lib/AST/
H A DDecl.cpp2725 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local
2726 if (!NewVT) in getTemplateInstantiationPattern()
2728 VarTemplate = NewVT; in getTemplateInstantiationPattern()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5251 MVT NewVT = in expandUnalignedRVVLoad() local
5253 assert(NewVT.isValid() && in expandUnalignedRVVLoad()
5282 MVT NewVT = in expandUnalignedRVVStore() local
5284 assert(NewVT.isValid() && in expandUnalignedRVVStore()
5286 StoredVal = DAG.getBitcast(NewVT, StoredVal); in expandUnalignedRVVStore()
12928 EVT NewVT = SrcVT.changeVectorElementType(NewEltVT); in narrowIndex() local
12931 SDValue NewShAmtVec = DAG.getConstant(ShAmtV, DL, NewVT); in narrowIndex()
12932 N = DAG.getNode(ISD::SHL, DL, NewVT, NewExt, NewShAmtVec); in narrowIndex()
15827 MVT NewVT = MVT::getIntegerVT(MemVT.getSizeInBits()); in PerformDAGCombine() local
15833 SDValue NewV = DAG.getConstant(NewC, DL, NewVT); in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1729 EVT NewVT) const { in shouldReduceLoadWidth() argument
1732 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()

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