| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineSSAUpdater.cpp | 124 Register NewVR = MRI->createVirtualRegister(RC); in InsertNewDef() local
125 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR); in InsertNewDef()
236 Register NewVR; in RewriteUse() local
239 NewVR = GetValueAtEndOfBlockInternal(SourceBB); in RewriteUse()
241 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
244 U.setReg(NewVR); in RewriteUse()
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| H A D | PeepholeOptimizer.cpp | 648 Register NewVR = MRI->createVirtualRegister(RC); in INITIALIZE_PASS_DEPENDENCY() local
650 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
655 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
828 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI() local
831 TII.get(TargetOpcode::PHI), NewVR); in insertPHI()
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| H A D | TargetInstrInfo.cpp | 1113 Register NewVR = MRI.createVirtualRegister(RC); in reassociateOps() local
1114 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in reassociateOps()
1131 BuildMI(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR) in reassociateOps()
1136 std::swap(RegA, NewVR); in reassociateOps()
1143 .addReg(NewVR, getKillRegState(KillNewVR)); in reassociateOps()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6765 Register NewVR = MRI.createVirtualRegister(RC); in genNeg() local
6772 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in genNeg()
6774 return NewVR; in genNeg()
6786 Register NewVR = in genFusedMultiplyAccNeg() local
6813 Register NewVR = in genFusedMultiplyIdxNeg() local
6910 .addReg(NewVR, getKillRegState(true)) in genSubAdd2SubSub()
7635 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
7682 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
7742 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
7762 Register NewVR = MRI.createVirtualRegister(RC); in genAlternativeCodeSequence() local
[all …]
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| H A D | AArch64ISelLowering.cpp | 25441 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
25451 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
25458 .addReg(NewVR); in insertCopiesSplitCSR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 1385 Register NewVR = MRI->createVirtualRegister(RC); in generateInserts() local
1386 RegMap[VR] = NewVR; in generateInserts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 9810 Register NewVR = in enforceOperandRCAlignment() local
9813 BuildMI(*BB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewVR) in enforceOperandRCAlignment()
9818 Op.setReg(NewVR); in enforceOperandRCAlignment()
9820 MI.addOperand(MachineOperand::CreateReg(NewVR, false, true)); in enforceOperandRCAlignment()
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| H A D | SIISelLowering.cpp | 2713 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
2716 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
2723 .addReg(NewVR); in insertCopiesSplitCSR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 22062 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
22072 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
22079 .addReg(NewVR); in insertCopiesSplitCSR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 57614 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
57624 BuildMI(*Entry, MBBI, MIMetadata(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
57631 .addReg(NewVR); in insertCopiesSplitCSR()
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