Searched refs:NewSrcVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2405 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp() local
2409 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT); in SplitVecRes_ExtendOp()
2411 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) { in SplitVecRes_ExtendOp()
2417 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0)); in SplitVecRes_ExtendOp()
2428 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0), in SplitVecRes_ExtendOp()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1515 EVT NewSrcVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumSrcElt / 2); in LowerEXTRACT_SUBVECTOR() local
1519 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42055 MVT NewSrcVT = MVT::getIntegerVT(BitWidth / 2); in SimplifyDemandedBitsForTargetNode() local
42057 TLO.DAG.getNode(ISD::TRUNCATE, SDLoc(Src), NewSrcVT, Src); in SimplifyDemandedBitsForTargetNode()
42058 MVT NewVT = MVT::getVectorVT(NewSrcVT, VT.getVectorNumElements() * 2); in SimplifyDemandedBitsForTargetNode()
42820 EVT NewSrcVT = in combineBitcastToBoolVector() local
42822 if (TLI.isTypeLegal(NewSrcVT)) in combineBitcastToBoolVector()
42824 combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, Subtarget)) in combineBitcastToBoolVector()
42833 EVT NewSrcVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in combineBitcastToBoolVector() local
42835 if (TLI.isTypeLegal(NewSrcVT)) in combineBitcastToBoolVector()
42837 combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, Subtarget)) in combineBitcastToBoolVector()
54953 EVT NewSrcVT = SrcVT.getDoubleNumVectorElementsVT(Ctx); in combineConcatVectorOps() local
[all …]
|