| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 163 Instruction *Ret = NewShift; in reassociateShiftAmtsOfTwoSameDirectionShifts()
165 Builder.Insert(NewShift); in reassociateShiftAmtsOfTwoSameDirectionShifts()
334 return NewShift; in dropRedundantMaskingOfLeftShiftInput()
336 Builder.Insert(NewShift); in dropRedundantMaskingOfLeftShiftInput()
431 if (auto *NewShift = cast_or_null<Instruction>( in commonShiftTransforms() local
433 return NewShift; in commonShiftTransforms()
821 Value *NewShift = in FoldShiftByConstant() local
823 NewShift->takeName(Op0BO); in FoldShiftByConstant()
852 return SelectInst::Create(Cond, NewOp, NewShift); in FoldShiftByConstant()
1185 Value *NewShift = Builder.CreateShl(X, Op1); in visitShl() local
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| H A D | InstCombineCompares.cpp | 1713 Value *NewShift = in foldICmpAndShift() local
1718 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift); in foldICmpAndShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3998 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine() local
4002 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
4022 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
4025 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
4032 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
4034 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
4082 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine() local
4084 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2581 Register NewShift = in applyCombineTruncOfShift() local
2587 replaceRegWith(MRI, Dst, NewShift); in applyCombineTruncOfShift()
2589 Builder.buildTrunc(Dst, NewShift); in applyCombineTruncOfShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2081 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask() local
2090 insertDAGNode(DAG, N, NewShift); in foldMaskedShiftToScaledMask()
2091 DAG.ReplaceAllUsesWith(N, NewShift); in foldMaskedShiftToScaledMask()
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| H A D | X86ISelLowering.cpp | 41826 SDValue NewShift = TLO.DAG.getNode( in SimplifyDemandedBitsForTargetNode() local
41829 return TLO.CombineTo(Op, NewShift); in SimplifyDemandedBitsForTargetNode()
47139 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical() local
47140 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask); in combineShiftRightLogical()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2697 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit() local
2699 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); in foldAddSubOfSignBit()
6904 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts() local
6905 return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); in foldLogicOfShifts()
9734 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant() local
9736 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
10570 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
10572 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); in visitSRL()
10580 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
10585 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL()
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| H A D | TargetLowering.cpp | 1854 SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp, in SimplifyDemandedBits() local
1857 TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift); in SimplifyDemandedBits()
1956 SDValue NewShift = in SimplifyDemandedBits() local
1959 Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift)); in SimplifyDemandedBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17460 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1, in PerformLongShiftCombine() local
17462 DAG.ReplaceAllUsesWith(N, NewShift.getNode()); in PerformLongShiftCombine()
17463 return NewShift; in PerformLongShiftCombine()
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