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Searched refs:NewOpcode (Results 1 – 25 of 47) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonVLIWPacketizer.cpp461 int NewOpcode; in promoteToDotNew() local
463 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
465 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
466 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
471 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
472 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
890 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : in canPromoteToDotNew() local
892 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp67 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
82 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
83 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
274 unsigned NewOpcode; in InsertVPTBlocks() local
276 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
278 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp109 bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
113 void applyCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
428 auto [LoadMI, NewOpcode] = MatchData; in applyCombineSignExtendInReg()
429 LoadMI->setDesc(TII.get(NewOpcode)); in applyCombineSignExtendInReg()
439 MachineInstr &MI, unsigned &NewOpcode) const { in matchCombine_s_mul_u64()
447 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32; in matchCombine_s_mul_u64()
453 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32; in matchCombine_s_mul_u64()
460 MachineInstr &MI, unsigned &NewOpcode) const { in applyCombine_s_mul_u64()
461 Helper.replaceOpcodeWith(MI, NewOpcode); in applyCombine_s_mul_u64()
H A DSIShrinkInstructions.cpp367 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
401 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma() local
418 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
421 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
424 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
447 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
450 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
453 NewOpcode = AMDGPU::V_MADMK_F16; in shrinkMadFma()
463 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) in shrinkMadFma()
466 if (AMDGPU::isTrue16Inst(NewOpcode) && !shouldShrinkTrue16(MI)) in shrinkMadFma()
[all …]
H A DGCNCreateVOPD.cpp76 int NewOpcode = in doReplace() local
79 assert(NewOpcode != -1 && in doReplace()
83 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
H A DR600MachineCFGStructurizer.cpp200 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
202 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
205 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
208 MachineBasicBlock::iterator I, int NewOpcode,
437 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
444 int NewOpcode, in insertInstrBefore() argument
447 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
457 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
469 MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) { in insertCondBranchBefore() argument
473 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL); in insertCondBranchBefore()
[all …]
H A DSIWholeQuadMode.cpp768 unsigned NewOpcode = 0; in splitBlock() local
771 NewOpcode = AMDGPU::S_AND_B32_term; in splitBlock()
774 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
777 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
780 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
785 if (NewOpcode) in splitBlock()
786 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
H A DSIOptimizeExecMasking.cpp578 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence() local
580 if (NewOpcode == -1) in optimizeVCMPSaveExecSequence()
600 VCmp.getDebugLoc(), TII->get(NewOpcode)); in optimizeVCMPSaveExecSequence()
H A DSIInstrInfo.cpp2552 unsigned NewOpcode = -1; in reMaterialize() local
2554 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM; in reMaterialize()
2556 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM; in reMaterialize()
2560 const MCInstrDesc &TID = get(NewOpcode); in reMaterialize()
6858 unsigned NewOpcode = getVALUOp(Inst); in moveToVALUImpl() local
6864 NewOpcode = AMDGPU::V_ADD_U64_PSEUDO; in moveToVALUImpl()
6867 NewOpcode = AMDGPU::V_SUB_U64_PSEUDO; in moveToVALUImpl()
6970 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALUImpl()
6976 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALUImpl()
6982 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALUImpl()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp524 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
525 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
530 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
588 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
594 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
599 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
612 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
616 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
619 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
623 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
H A DX86InstrInfo.cpp5121 unsigned NewOpcode = 0; in optimizeCompareInstr() local
5167 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || in optimizeCompareInstr()
5168 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) in optimizeCompareInstr()
5543 unsigned NewOpcode = 0; in ConvertALUrr2ALUri() local
5577 NewOpcode = X86::SHR64ri; in ConvertALUrr2ALUri()
5581 NewOpcode = X86::SHL64ri; in ConvertALUrr2ALUri()
5585 NewOpcode = X86::SAR64ri; in ConvertALUrr2ALUri()
5589 NewOpcode = X86::ROL64ri; in ConvertALUrr2ALUri()
5593 NewOpcode = X86::ROR64ri; in ConvertALUrr2ALUri()
5622 NewOpcode = X86::OR32ri; in ConvertALUrr2ALUri()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
264 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
266 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
451 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
469 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp173 int NewOpcode = -1; in encodeInstruction() local
176 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
177 if (NewOpcode == -1) in encodeInstruction()
178 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
181 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
184 if (NewOpcode == -1) in encodeInstruction()
185 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
187 if (NewOpcode != -1) { in encodeInstruction()
191 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp69 unsigned NewOpcode) const { in splitMove()
95 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
96 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
143 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
144 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
145 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
980 unsigned NewOpcode; in convertToThreeAddress() local
982 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
985 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
987 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
H A DSystemZFrameLowering.cpp727 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
731 if (!NewOpcode) { in emitEpilogue()
736 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
737 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
740 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
H A DSystemZInstrInfo.h189 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1661 std::string NewOpcode; in ParseInstruction() local
1663 NewOpcode = std::string(Name); in ParseInstruction()
1664 NewOpcode += '+'; in ParseInstruction()
1665 Name = NewOpcode; in ParseInstruction()
1668 NewOpcode = std::string(Name); in ParseInstruction()
1669 NewOpcode += '-'; in ParseInstruction()
1670 Name = NewOpcode; in ParseInstruction()
1676 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1684 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1734 unsigned NewOpcode = 0u; in eliminateFrameIndex() local
1782 NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex()
1783 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
1802 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1808 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
H A DPPCISelDAGToDAG.cpp7394 unsigned NewOpcode; in PeepholePPC64ZExt() local
7400 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
7401 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
7402 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
7403 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
7409 case PPC::OR: NewOpcode = PPC::OR8; break; in PeepholePPC64ZExt()
7411 case PPC::ORI: NewOpcode = PPC::ORI8; break; in PeepholePPC64ZExt()
7412 case PPC::ORIS: NewOpcode = PPC::ORIS8; break; in PeepholePPC64ZExt()
7413 case PPC::AND: NewOpcode = PPC::AND8; break; in PeepholePPC64ZExt()
7415 NewOpcode = PPC::ANDI8_rec; in PeepholePPC64ZExt()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp562 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
563 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp550 int NewOpcode; in expand_DestructiveOp() local
552 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
553 Opcode = NewOpcode; in expand_DestructiveOp()
555 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
556 Opcode = NewOpcode; in expand_DestructiveOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1113 int NewOpcode = in convertMIMGInst() local
1115 if (NewOpcode == -1) in convertMIMGInst()
1121 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; in convertMIMGInst()
1147 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; in convertMIMGInst()
1154 MI.setOpcode(NewOpcode); in convertMIMGInst()

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