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Searched refs:NegRHS (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprScalar.cpp3799 bool NegRHS = false; in tryEmitFMulAdd() local
3804 NegRHS = true; in tryEmitFMulAdd()
3822 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
3824 if (NegRHS) in tryEmitFMulAdd()
3826 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
3843 (RHSBinOp->use_empty() || NegRHS)) { in tryEmitFMulAdd()
3845 if (NegRHS) in tryEmitFMulAdd()
3847 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub ^ NegRHS, false); in tryEmitFMulAdd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1648 APFloat NegRHS = neg(CRHS->getValueAPF()); in combineFMinMaxLegacy() local
1649 if (NegRHS == CFalse->getValueAPF()) { in combineFMinMaxLegacy()
4802 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine() local
4805 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4940 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine() local
4943 NegRHS); in performFNegCombine()
H A DSIISelLowering.cpp14055 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFSubCombine() local
14057 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS); in performFSubCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7373 SDValue NegRHS = in getNegatedExpression() local
7379 if (!NegRHS || CostRHS > NegatibleCost::Neutral || in getNegatedExpression()
7383 RemoveDeadNode(NegRHS); in getNegatedExpression()
7388 return DAG.getSelect(DL, VT, Op.getOperand(0), NegLHS, NegRHS); in getNegatedExpression()
H A DDAGCombiner.cpp11244 SDValue NegRHS = TLI.getCheaperOrNeutralNegatedExpression( in combineMinNumMaxNum() local
11246 if (NegRHS) { in combineMinNumMaxNum()
11247 HandleSDNode NegRHSHandle(NegRHS); in combineMinNumMaxNum()
11248 if (NegRHS == False) { in combineMinNumMaxNum()