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Searched refs:NeedAlign (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterScavenging.cpp231 Align NeedAlign = TRI->getSpillAlign(RC); in spill() local
244 if (NeedSize > S || NeedAlign > A) in spill()
252 unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value()); in spill()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1906 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2() local
1912 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1923 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1953 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2() local
1958 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1966 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1992 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec() local
1994 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec()
2020 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec() local
2022 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec()
H A DHexagonISelLowering.cpp1955 Addr != 0 ? Align(1ull << llvm::countr_zero(Addr)) : NeedAlign; in validateConstPtrAlignment()
1956 if (HaveAlign >= NeedAlign) in validateConstPtrAlignment()
1977 << ", but the memory access requires " << NeedAlign.value(); in validateConstPtrAlignment()
3146 Align NeedAlign = Subtarget.getTypeAlignment(StoreTy); in LowerStore() local
3147 if (ClaimAlign < NeedAlign) in LowerStore()
3157 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).value(); in LowerUnalignedLoad() local
3159 if (HaveAlign >= NeedAlign) in LowerUnalignedLoad()
3179 if (!DoDefault && (2 * HaveAlign) == NeedAlign) { in LowerUnalignedLoad()
3196 assert(LoadTy.getSizeInBits() == 8*NeedAlign); in LowerUnalignedLoad()
3198 unsigned LoadLen = NeedAlign; in LowerUnalignedLoad()
[all …]
H A DHexagonInstrInfo.cpp1074 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) { in expandPostRAPseudo() argument
1077 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { in expandPostRAPseudo()
1078 return MMO->getAlign() >= NeedAlign; in expandPostRAPseudo()
1175 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1176 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1191 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1192 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1213 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1214 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1230 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
[all …]
H A DHexagonVectorCombine.cpp212 NeedAlign(HVC.getTypeAlignment(ValTy)) {} in AddrInfo()
220 Align NeedAlign; member
373 OS << "NeedAlign: " << AI.NeedAlign.value() << '\n'; in operator <<()
1450 getMaxOf(MoveInfos, [](const AddrInfo &AI) { return AI.NeedAlign; }); in realignGroup()
1451 Align MinNeeded = WithMaxNeeded.NeedAlign; in realignGroup()
H A DHexagonISelLowering.h368 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1803 bool NeedAlign; // Does argument declaration specify alignment? in LowerCall() local
1814 NeedAlign = PassAsArray; in LowerCall()
1823 NeedAlign = true; in LowerCall()
1838 NeedAlign = false; in LowerCall()
1855 if (NeedAlign) in LowerCall()