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Searched refs:Narrow (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td2968 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2976 def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
2977 (Narrow.KVT (Frag_su:$cc (Narrow.VT Narrow.RC:$src1),
2992 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2999 def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
3018 def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
3033 def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1),
3051 def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1),
3067 def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT (Narrow.BroadcastLdFrag addr:$src2)),
3486 def : Pat<(Narrow.VT (vselect (Narrow.KVT Narrow.KRCWM:$mask),
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H A DX86ISelLowering.cpp47999 SDValue Narrow = N->getOperand(0); in PromoteMaskArithmetic() local
48000 EVT NarrowVT = Narrow.getValueType(); in PromoteMaskArithmetic()
48003 SDValue Op = PromoteMaskArithmetic(Narrow.getNode(), VT, DAG, 0); in PromoteMaskArithmetic()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td1352 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1354 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1356 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1358 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1552 // Scalar Signed Saturating Extract Unsigned Narrow
1556 // Scalar Signed Saturating Extract Narrow
1560 // Scalar Unsigned Saturating Extract Narrow
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2135 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane() local
2140 if (Narrow) in SelectLoadLane()
2160 if (Narrow) in SelectLoadLane()
2173 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane() local
2178 if (Narrow) in SelectPostLoadLane()
2204 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
2212 if (Narrow) in SelectPostLoadLane()
2227 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane() local
2232 if (Narrow) in SelectStoreLane()
2255 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane() local
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H A DAArch64ISelLowering.cpp13636 SDValue Narrow; in LowerINSERT_SUBVECTOR() local
13639 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0); in LowerINSERT_SUBVECTOR()
13644 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1); in LowerINSERT_SUBVECTOR()
13647 return getSVESafeBitCast(VT, Narrow, DAG); in LowerINSERT_SUBVECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6039 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorLoadLaneIntrinsic() local
6046 if (Narrow) { in selectVectorLoadLaneIntrinsic()
6071 {Narrow ? DstOp(&AArch64::FPR128RegClass) in selectVectorLoadLaneIntrinsic()
6078 if (Narrow && in selectVectorLoadLaneIntrinsic()
6107 bool Narrow = Ty.getSizeInBits() == 64; in selectVectorStoreLaneIntrinsic() local
6113 if (Narrow) in selectVectorStoreLaneIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2570 // Narrow 2-register operations.
2579 // Narrow 2-register intrinsics.
3232 // Narrow shift by immediate.
4223 // Neon Shift Narrow operations,
4293 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
5101 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
6018 // VSHRN : Vector Shift Right and Narrow
6045 // VRSHRN : Vector Rounding Shift Right and Narrow
6063 // VQSHRN : Vector Saturating Shift Right and Narrow
6069 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
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H A DARMScheduleSwift.td577 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
/freebsd-14.2/contrib/openbsm/
H A DNEWS463 - Narrow set of symbols and defines that are exposed in user space: don't
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td435 // Vector Saturating Narrow
441 // Vector Saturating Extract and Unsigned Narrow