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Searched refs:MinVT (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1741 MVT MinVT = TLI.getRegisterType(MVT::i32); in GetReturnInfo() local
1742 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1743 VT = MinVT; in GetReturnInfo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp993 EVT MinVT = getRegisterType(Context, ReturnMVT); in getTypeForExtReturn() local
994 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4663 EVT MinVT = getRegisterType(MVT::i32); in getTypeForExtReturn() local
4664 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4041 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32); in getTypeForExtReturn() local
4042 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp13704 EVT MinVT = N0.getValueType(); in visitZERO_EXTEND() local
13712 Op = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
13724 SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
23899 EVT MinVT = SVT; in visitCONCAT_VECTORS() local
23907 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
23918 Opnds.append(NumElts, DAG.getUNDEF(MinVT)); in visitCONCAT_VECTORS()
23927 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i))); in visitCONCAT_VECTORS()
H A DTargetLowering.cpp4542 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); in SimplifySetCC() local
4543 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
4545 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); in SimplifySetCC()
4550 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); in SimplifySetCC()