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Searched refs:MidVT (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4926 MVT MidVT = OldEltsPerNewElt == 1 in getPromotedVectorElementType() local
4929 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType()
4930 return MidVT; in getPromotedVectorElementType()
5417 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
5452 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
5453 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
5473 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode()
5499 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
5510 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode()
5542 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val); in PromoteNode()
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H A DLegalizeFloatTypes.cpp568 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local
573 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp4155 EVT MidVT = VT.isVector() ? in performTruncateCombine() local
4159 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout()); in performTruncateCombine()
4160 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
4169 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18145 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local
18146 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine()
18151 MidVT, dl, in performConcatVectorsCombine()
18152 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
18153 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp49745 EVT MidVT = VT.changeVectorElementType(MVT::i16); in combineTruncateWithSat() local
49746 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()