Searched refs:MidRegLo (Results 1 – 1 of 1) sorted by relevance
8051 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local8055 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32_e64), MidRegLo) in splitScalar64BitBFE()8062 .addReg(MidRegLo); in splitScalar64BitBFE()8065 .addReg(MidRegLo) in splitScalar64BitBFE()