Searched refs:MidReg2 (Results 1 – 1 of 1) sorted by relevance
8126 Register MidReg2 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitCountOp() local8132 BuildMI(MBB, MII, DL, InstDesc, MidReg2).add(SrcRegSub1); in splitScalar64BitCountOp()8135 .addReg(IsCtlz ? MidReg1 : MidReg2) in splitScalar64BitCountOp()8141 .addReg(IsCtlz ? MidReg2 : MidReg1); in splitScalar64BitCountOp()