Searched refs:MidReg1 (Results 1 – 1 of 1) sorted by relevance
8125 Register MidReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitCountOp() local8130 BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0); in splitScalar64BitCountOp()8135 .addReg(IsCtlz ? MidReg1 : MidReg2) in splitScalar64BitCountOp()8141 .addReg(IsCtlz ? MidReg2 : MidReg1); in splitScalar64BitCountOp()