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Searched refs:MaskReg (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp316 .addReg(MaskReg); in insertMaskedMerge()
334 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
475 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
491 .addReg(MaskReg); in expandAtomicMinMaxOp()
534 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
573 Register MaskReg, in tryToFoldBNEOnCmpXchgResult() argument
582 if (MaskReg.isValid()) { in tryToFoldBNEOnCmpXchgResult()
606 if (MaskReg.isValid()) { in tryToFoldBNEOnCmpXchgResult()
690 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
696 .addReg(MaskReg); in expandAtomicCmpXchg()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp221 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
223 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
224 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
232 .addReg(MaskReg); in insertMaskedMerge()
247 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
386 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
398 .addReg(MaskReg); in expandAtomicMinMaxOp()
444 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
537 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
544 .addReg(MaskReg); in expandAtomicCmpXchg()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1466 const Register MaskReg = I.getOperand(2).getReg(); in selectInverseBallot() local
1468 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(MaskReg); in selectInverseBallot()
2952 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2954 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2960 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2967 APInt MaskOnes = KB->getKnownOnes(MaskReg).zext(64); in selectG_PTRMASK()
2978 .addReg(MaskReg) in selectG_PTRMASK()
2995 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
3004 .addReg(MaskReg); in selectG_PTRMASK()
3032 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
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H A DAMDGPURegisterBankInfo.cpp4789 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4790 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
4791 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4798 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4799 unsigned MaskSize = MRI.getType(MaskReg).getSizeInBits(); in getInstrMapping()
4800 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4816 Register MaskReg = MI.getOperand(2).getReg(); in getInstrMapping() local
4817 unsigned MaskBank = getRegBankID(MaskReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
H A DSIISelLowering.cpp5260 Register MaskReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
5262 const bool IsVALU = TRI->isVectorRegister(MRI, MaskReg); in EmitInstrWithCustomInserter()
5265 MaskReg = TII->readlaneVGPRToSGPR(MaskReg, MI, MRI); in EmitInstrWithCustomInserter()
5268 BuildMI(*BB, &MI, DL, TII->get(AMDGPU::COPY), DstReg).addReg(MaskReg); in EmitInstrWithCustomInserter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp230 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
231 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
232 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
H A DLegalizerHelper.cpp7956 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] = in lowerSelect()
7973 Register MaskElt = MaskReg; in lowerSelect()
7986 MaskReg = ShufSplat.getReg(0); in lowerSelect()
7994 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
7995 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h430 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
H A DAArch64InstrInfo.cpp1357 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1359 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12079 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
12155 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
12169 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12170 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
12178 .addReg(MaskReg); in EmitPartwordAtomicBinary()
13074 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
13159 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
13164 .addReg(MaskReg); in EmitInstrWithCustomInserter()
13167 .addReg(MaskReg); in EmitInstrWithCustomInserter()
13175 .addReg(MaskReg); in EmitInstrWithCustomInserter()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp3157 Register MaskReg = I.getOperand(2).getReg(); in select() local
3158 std::optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6145 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
6155 .addReg(MaskReg, MaskState) in expandPostRAPseudo()