| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 279 unsigned &MaskLen) { in isShiftedMask_32() argument
283 MaskLen = llvm::popcount(Value); in isShiftedMask_32()
292 unsigned &MaskLen) { in isShiftedMask_64() argument
296 MaskLen = llvm::popcount(Value); in isShiftedMask_64()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 500 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
502 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
508 MaskLen = Ones; in isShiftedMask()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 573 unsigned MaskIdx, MaskLen;
575 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
576 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
581 unsigned MaskIdx, MaskLen;
583 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
584 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
585 return CurDAG->getTargetConstant(MaskIdx + MaskLen - 1, SDLoc(N),
591 unsigned MaskIdx, MaskLen;
593 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
594 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
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| H A D | LoongArchISelLowering.cpp | 2201 unsigned MaskIdx, MaskLen; in performSRLCombine() local
2208 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
2216 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
2219 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
2362 unsigned MaskIdx, MaskLen; in performORCombine() local
2365 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
2367 CNShamt->getZExtValue() + MaskLen <= ValBits) { in performORCombine()
2374 DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT), in performORCombine()
2389 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
2398 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2067 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2068 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2111 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2112 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
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| H A D | X86ISelDAGToDAG.cpp | 2135 unsigned MaskIdx, MaskLen; in foldMaskAndShiftToScale() local
2136 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskAndShiftToScale()
2138 unsigned MaskLZ = 64 - (MaskIdx + MaskLen); in foldMaskAndShiftToScale()
2234 unsigned MaskIdx, MaskLen; in foldMaskedShiftToBEXTR() local
2235 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskedShiftToBEXTR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1086 unsigned MaskLen = SM.Mask.size(); in getOutputSegmentMap() local
1087 assert(MaskLen % SegLen == 0); in getOutputSegmentMap()
1088 SmallVector<unsigned, 4> Map(MaskLen / SegLen); in getOutputSegmentMap()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 728 unsigned LowZBits, MaskLen; in SelectShiftedRegisterFromAnd() local
729 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
739 if (LowZBits <= ShiftAmtC || (BitWidth != LowZBits + MaskLen)) in SelectShiftedRegisterFromAnd()
754 if (LHSOpcode == ISD::SRA && (BitWidth != (LowZBits + MaskLen))) in SelectShiftedRegisterFromAnd()
758 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) in SelectShiftedRegisterFromAnd()
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| H A D | AArch64ISelLowering.cpp | 16403 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
16404 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
16408 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
16409 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4057 unsigned MaskIdx, MaskLen; in performSrlCombine() local
4058 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13845 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13846 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13850 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13851 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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