| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1254 SDValue MaskLo, MaskHi; in SplitMask() local
1281 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp() local
1315 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp() local
1952 SDValue MaskLo, MaskHi; in SplitVecRes_VP_LOAD() local
2107 SDValue MaskLo, MaskHi; in SplitVecRes_MLOAD() local
2198 SDValue MaskLo, MaskHi; in SplitVecRes_Gather() local
2334 SDValue MaskLo, MaskHi; in SplitVecRes_UnaryOp() local
3200 SDValue MaskLo, MaskHi; in SplitVecOp_VP_REDUCE() local
3456 SDValue MaskLo, MaskHi; in SplitVecOp_VP_STORE() local
3608 SDValue MaskLo, MaskHi; in SplitVecOp_MSTORE() local
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1523 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1524 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1528 EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi); in PromoteIntRes_TRUNCATE()
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| H A D | TargetLowering.cpp | 2377 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2384 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) in SimplifyDemandedBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 3042 Register MaskHi = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
3045 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi) in selectG_PTRMASK()
3049 .addReg(MaskHi); in selectG_PTRMASK()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23404 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23405 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
23415 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23416 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
23440 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23442 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi); in LowerVSETCC()
23444 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 5789 auto [MaskLo, MaskHi] = DAG.SplitVector(Op.getOperand(2), DL); in SplitVectorReductionOp()
5797 {ResLo, Hi, MaskHi, EVLHi}, Op->getFlags()); in SplitVectorReductionOp()
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