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Searched refs:Mask1 (Results 1 – 15 of 15) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp293 int Mask0, Mask1; in convertLogicOp() local
296 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
302 Mask = Mask0 & Mask1; in convertLogicOp()
305 Mask = Mask0 | Mask1; in convertLogicOp()
308 Mask = Mask0 ^ Mask1; in convertLogicOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp235 VPValue *Mask1 = getPredicatedMask(Region1); in mergeReplicateRegionsIntoSuccessors() local
237 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegionsIntoSuccessors()
240 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegionsIntoSuccessors()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp1005 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
1007 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
1009 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
1012 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSystemRegister.td45 // Mask1 Mask2 Mask3 Enc12, Name
H A DARMISelLowering.cpp6083 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
6085 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp2112 SmallVector<int, 16> Mask1; in foldSelectShuffleOfSelectShuffle() local
2113 ShufOp->getShuffleMask(Mask1); in foldSelectShuffleOfSelectShuffle()
2114 assert(Mask1.size() == NumElts && "Vector size changed with select shuffle"); in foldSelectShuffleOfSelectShuffle()
2119 ShuffleVectorInst::commuteShuffleMask(Mask1, NumElts); in foldSelectShuffleOfSelectShuffle()
2128 NewMask[i] = Mask[i] < (signed)NumElts ? Mask[i] : Mask1[i]; in foldSelectShuffleOfSelectShuffle()
H A DInstCombineCalls.cpp2678 uint64_t Mask1 = computeKnownBits(Mask, 0, II).One.getZExtValue(); in visitCallInst() local
2680 uint64_t C = Bytes1 & Mask1; in visitCallInst()
H A DInstCombineCompares.cpp3533 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3538 return new ICmpInst(Pred, Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2098 auto same = [](ArrayRef<int> Mask1, ArrayRef<int> Mask2) -> bool { in contracting() argument
2099 return Mask1 == Mask2; in contracting()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp9180 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandBITREVERSE() local
9201 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
9202 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
9245 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandVPBITREVERSE() local
9276 DAG.getConstant(Mask1, dl, VT), Mask, EVL); in expandVPBITREVERSE()
9277 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT), in expandVPBITREVERSE()
H A DDAGCombiner.cpp7605 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
7606 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
7609 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
24615 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
24626 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
24634 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
24642 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6550 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
6551 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5753 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
5755 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
5761 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
5763 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
47197 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
47203 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
47204 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
47251 SmallVector<int> Mask0, Mask1; in combineHorizOpWithShuffle() local
47255 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
47262 scaleShuffleElements(Mask1, 2, ScaledMask1)) { in combineHorizOpWithShuffle()
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/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp16720 Value *Mask1 = Builder.CreateCall(Lvs, Op0, "mask1"); in EmitPPCBuiltinExpr() local
16724 Value *AllElts = Builder.CreateCall(Vperm, {Op0, Op1, Mask1}, "shuffle1"); in EmitPPCBuiltinExpr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12141 SDValue Mask1 = Tbl1->getOperand(3); in tryToConvertShuffleOfTbl2ToTbl4() local
12146 TBLMaskParts[I] = Mask1->getOperand(ShuffleMask[I]); in tryToConvertShuffleOfTbl2ToTbl4()