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Searched refs:MOReg (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeVGPRLiveRange.cpp238 Register MOReg = MO.getReg(); in collectCandidateRegisters() local
240 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectCandidateRegisters()
244 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
253 LiveVariables::VarInfo &VI = LV->getVarInfo(MOReg); in collectCandidateRegisters()
254 if (!VI.isLiveIn(*Endif, MOReg, *MRI)) { in collectCandidateRegisters()
255 KillsInElse.insert(MOReg); in collectCandidateRegisters()
364 Register MOReg = MO.getReg(); in collectWaterfallCandidateRegisters() local
366 if (MOReg.isPhysical() || !TRI->isVectorRegister(*MRI, MOReg)) in collectWaterfallCandidateRegisters()
376 LiveVariables::VarInfo &OldVarInfo = LV->getVarInfo(MOReg); in collectWaterfallCandidateRegisters()
380 OldVarInfo.isLiveIn(*Succ, MOReg, *MRI)) { in collectWaterfallCandidateRegisters()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp892 if (!MOReg) in rescheduleMIBelowKill()
895 Defs.push_back(MOReg); in rescheduleMIBelowKill()
897 Uses.push_back(MOReg); in rescheduleMIBelowKill()
899 Kills.push_back(MOReg); in rescheduleMIBelowKill()
935 if (!MOReg) in rescheduleMIBelowKill()
950 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg)) || in rescheduleMIBelowKill()
1073 if (!MOReg) in rescheduleKillAboveMI()
1080 Uses.push_back(MOReg); in rescheduleKillAboveMI()
1084 Defs.push_back(MOReg); in rescheduleKillAboveMI()
1109 if (!MOReg) in rescheduleKillAboveMI()
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H A DDetectDeadLanes.cpp112 Register MOReg = MO.getReg(); in addUsedLanesOnOperand() local
113 if (!MOReg.isVirtual()) in addUsedLanesOnOperand()
119 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); in addUsedLanesOnOperand()
121 unsigned MORegIdx = Register::virtReg2Index(MOReg); in addUsedLanesOnOperand()
296 Register MOReg = MO.getReg(); in determineInitialDefinedLanes() local
297 if (!MOReg) in determineInitialDefinedLanes()
301 if (MOReg.isPhysical()) { in determineInitialDefinedLanes()
306 assert(MOReg.isVirtual()); in determineInitialDefinedLanes()
307 if (MRI->hasOneDef(MOReg)) { in determineInitialDefinedLanes()
445 Register MOReg = MO.getReg(); in isUndefInput() local
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H A DLiveVariables.cpp505 Register MOReg = MO.getReg(); in runOnInstr() local
507 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg))) in runOnInstr()
510 UseRegs.push_back(MOReg); in runOnInstr()
515 if (MOReg.isPhysical() && !MRI->isReserved(MOReg)) in runOnInstr()
517 DefRegs.push_back(MOReg); in runOnInstr()
523 for (unsigned MOReg : UseRegs) { in runOnInstr() local
526 else if (!MRI->isReserved(MOReg)) in runOnInstr()
527 HandlePhysRegUse(MOReg, MI); in runOnInstr()
535 for (unsigned MOReg : DefRegs) { in runOnInstr() local
537 HandleVirtRegDef(MOReg, MI); in runOnInstr()
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H A DMachineInstrBundle.cpp353 Register MOReg = MO.getReg(); in AnalyzePhysRegInBundle() local
354 if (!MOReg || !MOReg.isPhysical()) in AnalyzePhysRegInBundle()
357 if (!TRI->regsOverlap(MOReg, Reg)) in AnalyzePhysRegInBundle()
360 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg); in AnalyzePhysRegInBundle()
H A DMachineInstr.cpp1020 Register MOReg = MO.getReg(); in findRegisterUseOperandIdx() local
1021 if (!MOReg) in findRegisterUseOperandIdx()
1023 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
1074 Register MOReg = MO.getReg(); in findRegisterDefOperandIdx() local
1075 bool Found = (MOReg == Reg); in findRegisterDefOperandIdx()
1078 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1080 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
2017 Register MOReg = MO.getReg(); in addRegisterDead() local
2018 if (!MOReg) in addRegisterDead()
2021 if (MOReg == Reg) { in addRegisterDead()
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H A DTargetInstrInfo.cpp1605 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs() local
1606 if (MOReg.isUndef()) in getRegSequenceInputs()
1612 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1630 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs() local
1631 if (MOReg.isUndef()) in getExtractSubregInputs()
1637 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1638 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
H A DMachineCSE.cpp393 Register MOReg = MO.getReg(); in PhysRegDefsReach() local
394 if (MOReg.isVirtual()) in PhysRegDefsReach()
396 if (PhysRefs.count(MOReg.asMCReg())) in PhysRegDefsReach()
H A DMachineLICM.cpp1101 Register MOReg = MO.getReg(); in HasHighOperandLatency() local
1102 if (MOReg != Reg) in HasHighOperandLatency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp443 Register MOReg = MO.getReg(); in PrintAsmOperand() local
446 if (!SP::IntPairRegClass.contains(MOReg)) { in PrintAsmOperand()
451 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even, in PrintAsmOperand()
453 if (!MOReg) { in PrintAsmOperand()
465 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
466 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd); in PrintAsmOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp568 Register MOReg = MO.getReg(); in restoreLatency() local
570 IsSameOrSubReg = (MOReg == DepR); in restoreLatency()
572 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp143 if (Register MOReg = MO.getReg()) { in getRegReferences() local
144 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5464 const MachineOperand *MOReg = &MI.getOperand(1); in getRegSequenceLikeInputs() local
5465 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5466 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5467 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5469 MOReg = &MI.getOperand(2); in getRegSequenceLikeInputs()
5470 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5471 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5490 const MachineOperand &MOReg = MI.getOperand(2); in getExtractSubregLikeInputs() local
5491 if (MOReg.isUndef()) in getExtractSubregLikeInputs()
5493 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
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